vt52-fpga  1.0.0 Initial
vt52-fpga is a serial terminal implemented on a FPGA
vt52.v
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1 module top (input pin_clk,
2  output wire vga_clk,
3  output wire vga_blank,
4  output wire hsync,
5  output wire vsync,
6  output wire [7:0]vga_r,
7  output wire [7:0]vga_g,
8  output wire [7:0]vga_b,
9  output wire pin_led,
10  input ps2_data,
11  input ps2_clk,
12  inout pin_usb_p,
13  inout pin_usb_n,
14  output wire pin_pu,
15  input wire uart_rxd,
16  output wire uart_txd
17 
18  );
19  localparam ROWS = 24;
20  localparam COLS = 80;
21  localparam ROW_BITS = 5;
22  localparam COL_BITS = 7;
23  localparam ADDR_BITS = 11;
24 
25  // clock generator outputs
26  wire clk_usb, reset_usb;
27  wire clk_vga, reset_vga;
28 
29  // scroll
30  wire [ADDR_BITS-1:0] new_first_char;
31  wire new_first_char_wen;
32  wire [ADDR_BITS-1:0] first_char;
33  // cursor
34  wire [ROW_BITS-1:0] new_cursor_y;
35  wire [COL_BITS-1:0] new_cursor_x;
36  wire new_cursor_wen;
37  wire cursor_blink_on;
38  wire [ROW_BITS-1:0] cursor_y;
39  wire [COL_BITS-1:0] cursor_x;
40  // char buffer
41  wire [7:0] new_char;
42  wire [ADDR_BITS-1:0] new_char_address;
43  wire new_char_wen;
44  wire [ADDR_BITS-1:0] char_address;
45  wire [7:0] char;
46  // char rom
47  wire graphic_mode_state;
48  wire graphic_mode;
49  wire [11:0] char_rom_address;
50  wire [7:0] char_rom_data;
51 
52  // video generator
53  wire vblank, hblank;
54  wire video;
55  assign vga_clk = clk_vga;
56  assign vga_blank = ~hblank; // background colour always black if vblank added as well
57 
58  // uart input/output
59  wire [7:0] uart_out_data;
60  wire uart_out_valid;
61  wire uart_out_ready;
62 
63  wire [7:0] uart_in_data;
64  wire uart_in_valid;
65  wire uart_in_ready;
66 
67  wire det_reset;
68  assign pin_led = det_reset;
69 
70  assign uart_rts = 1'b1;
71 
72  // led follows the cursor blink
73 // assign pin_led = cursor_blink_on;
74 
75  // USB host detect and reset
76  assign pin_pu = 1'b1;
77 
78  // amber text on dark blue, alt full drive {8{video}};
79  assign vga_r = (video) ? 240 : 0;
80  assign vga_g = (video) ? 240 : 0;
81  assign vga_b = (video) ? 0 : 64;
82 
83  assign graphic_mode_state = graphic_mode;
84 
85  //
86  // Instantiate all modules
87  //
88  clock_generator clock_generator(.clk(pin_clk),
89  .clk_usb(clk_usb),
90  .reset_usb(reset_usb),
91  .clk_vga(clk_vga),
92  .reset_vga(reset_vga)
93  );
94 
95  keyboard keyboard(.clk(clk_usb),
96  .reset(reset_usb),
97  .ps2_data(ps2_data),
98  .ps2_clk(ps2_clk),
99  .data(uart_in_data),
100  .valid(uart_in_valid),
101  .ready(uart_in_ready)
102  );
103 
104  cursor #(.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS))
105  cursor(.clk(clk_usb),
106  .reset(reset_usb),
107  .tick(vblank),
108  .x(cursor_x),
109  .y(cursor_y),
110  .blink_on(cursor_blink_on),
111  .new_x(new_cursor_x),
112  .new_y(new_cursor_y),
113  .wen(new_cursor_wen)
114  );
115 
116  simple_register #(.SIZE(ADDR_BITS))
117  scroll_register(.clk(clk_usb),
118  .reset(reset_usb),
119  .idata(new_first_char),
120  .wen(new_first_char_wen),
121  .odata(first_char)
122  );
123 
124  char_buffer char_buffer(.clk(clk_usb),
125  .din(new_char),
126  .waddr(new_char_address),
127  .wen(new_char_wen),
128  .raddr(char_address),
129  .dout(char),
130  .graphic_mode(graphic_mode)
131  );
132 
133  char_rom char_rom(.clk(clk_usb),
134  .addr(char_rom_address),
135  .dout_(char_rom_data)
136 // .graphic_mode(graphic_mode)
137  );
138 
139  video_generator #(.ROWS(ROWS),
140  .COLS(COLS),
141  .ROW_BITS(ROW_BITS),
142  .COL_BITS(COL_BITS),
143  .ADDR_BITS(ADDR_BITS))
144  video_generator(.clk(clk_vga),
145  .reset(reset_vga),
146  .hsync(hsync),
147  .vsync(vsync),
148  .video(video),
149  .hblank(hblank),
150  .vblank(vblank),
151  .cursor_x(cursor_x),
152  .cursor_y(cursor_y),
153  .cursor_blink_on(cursor_blink_on),
154  .first_char(first_char),
155  .char_buffer_address(char_address),
156  .char_buffer_data(char),
157  .char_rom_address(char_rom_address),
158  .char_rom_data(char_rom_data)
159  );
160 
161 `ifdef ALT_UART
162 
163  uart uart_inst (
164  .clk(clk_usb),
165  .rst(reset_usb),
166  // AXI input
167  .s_axis_tdata(uart_in_data),
168  .s_axis_tvalid(uart_in_valid),
169  .s_axis_tready(uart_in_ready),
170  // AXI output
171  .m_axis_tdata(uart_out_data),
172  .m_axis_tvalid(uart_out_valid),
173  .m_axis_tready(uart_out_ready),
174  // uart
175  .rxd(uart_rxd),
176  .txd(uart_txd),
177  // status
178  .tx_busy(),
179  .rx_busy(),
180  .rx_overrun_error(),
181  .rx_frame_error(),
182  // configuration
183 // .prescale(125000000/(9600*8)) // 9600 bps
184 // .prescale(125000000/(115200*8)) // 115200 bps
185  .prescale(48000000/(115200*8)) // 115200 bps
186 // .prescale(48000000/(9600*8)) // 9600 bps
187 // .prescale(52) // 115200 bps with 48 mhz clock
188  );
189 
190 `else
191 
192  usb_uart uart(.clk_48mhz(clk_usb),
193  .reset(reset_usb),
194  // usb pins
195  .pin_usb_p(pin_usb_p),
196  .pin_usb_n(pin_usb_n),
197  // uart pipeline in (keyboard->usb)
198  .uart_in_data(uart_in_data),
199  .uart_in_valid(uart_in_valid),
200  .uart_in_ready(uart_in_ready),
201  // uart pipeline out (usb->command_handler)
202  .uart_out_data(uart_out_data),
203  .uart_out_valid(uart_out_valid),
204  .uart_out_ready(uart_out_ready),
205  .det_reset(det_reset)
206  );
207 `endif
208 
209  command_handler #(.ROWS(ROWS),
210  .COLS(COLS),
211  .ROW_BITS(ROW_BITS),
212  .COL_BITS(COL_BITS),
213  .ADDR_BITS(ADDR_BITS))
214  command_handler(.clk(clk_usb),
215  .reset(reset_usb),// || det_reset),
216  .data(uart_out_data),
217  .valid(uart_out_valid),
218  .ready(uart_out_ready),
219  .new_first_char(new_first_char),
220  .new_first_char_wen(new_first_char_wen),
221  .new_char(new_char),
222  .new_char_address(new_char_address),
223  .new_char_wen(new_char_wen),
224  .new_cursor_x(new_cursor_x),
225  .new_cursor_y(new_cursor_y),
226  .new_cursor_wen(new_cursor_wen),
227  .graphic_mode(graphic_mode)
228  );
229 
230  endmodule
command_handler
module command_handler(input clk, input reset, input[8] data, input valid, output ready, output[ADDR_BITS-1:0] new_first_char, output new_first_char_wen, output[8] new_char, output[ADDR_BITS-1:0] new_char_address, output new_char_wen, output[COL_BITS-1:0] new_cursor_x, output[ROW_BITS-1:0] new_cursor_y, output new_cursor_wen, output graphic_mode)
Definition: command_handler.v:10
usb_uart
module usb_uart(input clk_48mhz, input reset, output usb_p_tx, output usb_n_tx, input usb_p_rx, input usb_n_rx, output usb_tx_en, input[8] uart_in_data, input uart_in_valid, output uart_in_ready, output[8] uart_out_data, output uart_out_valid, input uart_out_ready, output[11:0] debug)
Definition: usb_uart.v:126
simple_register
module simple_register(input wire clk, input wire reset, input wire< SIZE-1:0 > idata, input wire wen, output reg< SIZE-1:0 > odata)
Basic register with synchronous set & reset.
Definition: simple_register.v:6
top
module top(input pin_clk, output wire vga_clk, output wire vga_blank, output wire hsync, output wire vsync, output wire< 7:0 > vga_r, output wire< 7:0 > vga_g, output wire< 7:0 > vga_b, output wire pin_led, input ps2_data, input ps2_clk, inout pin_usb_p, inout pin_usb_n, output wire pin_pu, input wire uart_rxd, output wire uart_txd)
Definition: vt52.v:1
cursor
module cursor(input clk, input reset, input tick, output wire< COL_BITS-1:0 > x, output wire< ROW_BITS-1:0 > y, output wire blink_on, input[COL_BITS-1:0] new_x, input[ROW_BITS-1:0] new_y, input wen)
Cursor (position and blinking)
Definition: cursor.v:7
uart
module uart(parameter DATA_WIDTH=8)(input wire clk
clock_generator
module clock_generator(input clk, output clk_usb, output reset_usb, output clk_vga, output reset_vga)
Definition: clock_generator.v:2
char_buffer
module char_buffer(input wire clk, input wire< 7:0 > din, input wire< ADDR_BITS-1:0 > waddr, input wire wen, input wire< ADDR_BITS-1:0 > raddr, output reg< 7:0 > dout, input wire graphic_mode)
Char Buffer RAM (1920x8) (24 lines of 80 characters)
Definition: char_buffer.v:8
char_rom
module char_rom(input clk, input[11:0] addr, output[8] dout_)
Character Font ROM (4kx8) This could be a RAM to allow font modifications, but not for now latin-1 su...
Definition: char_rom.v:10
video_generator
module video_generator(input clk, input reset, output reg hsync, output reg vsync, output reg video, output reg hblank, output reg vblank, input[COL_BITS-1:0] cursor_x, input[ROW_BITS-1:0] cursor_y, input cursor_blink_on, input[ADDR_BITS-1:0] first_char, output wire< ADDR_BITS-1:0 > char_buffer_address, input[8] char_buffer_data, output wire< 11:0 > char_rom_address, input[8] char_rom_data, input graphic_mode_state)
80x24 char generator (8x16 char size) & sync generator
Definition: video_generator.v:13
keyboard
module keyboard(input clk, input reset, input ps2_data, input ps2_clk, output reg< 7:0 > data, output reg valid, input ready)
Definition: keyboard.v:2
s_axis_tvalid
module input wire input wire< DATA_WIDTH-1:0 > input wire s_axis_tvalid
Definition: uart.v:44
txd
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire txd
Definition: uart.v:58
m_axis_tdata
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > m_axis_tdata
Definition: uart.v:50
prescale
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire output wire input wire< 15:0 > prescale
Definition: uart.v:73
rst
module input wire rst
Definition: uart.v:38
tx_busy
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire tx_busy
Definition: uart.v:63
s_axis_tready
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire s_axis_tready
Definition: uart.v:45
rx_frame_error
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire output wire rx_frame_error
Definition: uart.v:66
m_axis_tvalid
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire m_axis_tvalid
Definition: uart.v:51
m_axis_tready
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire m_axis_tready
Definition: uart.v:52
rx_busy
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire rx_busy
Definition: uart.v:64
s_axis_tdata
module input wire input wire< DATA_WIDTH-1:0 > s_axis_tdata
Definition: uart.v:43
rx_overrun_error
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire rx_overrun_error
Definition: uart.v:65
rxd
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire rxd
Definition: uart.v:57