vt52-fpga  1.0.0 Initial
vt52-fpga is a serial terminal implemented on a FPGA
Functions | Variables
uart.v File Reference

Go to the source code of this file.

Functions

module uart (parameter DATA_WIDTH=8)(input wire clk
 
uart_rx< .DATA_WIDTH(DATA_WIDTH)> uart_rx_inst (.clk(clk),.rst(rst),.m_axis_tdata(m_axis_tdata),.m_axis_tvalid(m_axis_tvalid),.m_axis_tready(m_axis_tready),.rxd(rxd),.busy(rx_busy),.overrun_error(rx_overrun_error),.frame_error(rx_frame_error),.prescale(prescale))
 

Variables

module input wire rst
 
module input wire input wire< DATA_WIDTH-1:0 > s_axis_tdata
 
module input wire input wire< DATA_WIDTH-1:0 > input wire s_axis_tvalid
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire s_axis_tready = s_axis_tready_reg
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > m_axis_tdata = m_axis_tdata_reg
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire m_axis_tvalid = m_axis_tvalid_reg
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire m_axis_tready
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire rxd
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire txd = txd_reg
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire tx_busy
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire rx_busy
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire rx_overrun_error
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire output wire rx_frame_error
 
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire output wire input wire< 15:0 > prescale
 

Function Documentation

◆ uart_rx_inst()

uart_rx< .DATA_WIDTH(DATA_WIDTH)> uart_rx_inst ( .  clkclk,
.  rstrst,
.  m_axis_tdatam_axis_tdata,
.  m_axis_tvalidm_axis_tvalid,
.  m_axis_treadym_axis_tready,
.  rxdrxd,
.  busyrx_busy,
.  overrun_errorrx_overrun_error,
.  frame_errorrx_frame_error,
.  prescaleprescale 
)

Variable Documentation

◆ m_axis_tdata

assign m_axis_tdata = m_axis_tdata_reg

Definition at line 50 of file uart.v.

Referenced by top().

◆ m_axis_tready

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire m_axis_tready

Definition at line 52 of file uart.v.

Referenced by top().

◆ m_axis_tvalid

assign m_axis_tvalid = m_axis_tvalid_reg

Definition at line 51 of file uart.v.

Referenced by top().

◆ prescale

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire input wire output wire output wire output wire output wire output wire input wire<15:0> prescale
Initial value:
{
uart_tx <
.DATA_WIDTH(DATA_WIDTH)
>
uart_tx_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.txd(txd),
.busy(tx_busy),
.prescale(prescale)
)
uart_tx
module uart_tx(parameter DATA_WIDTH=8)(input wire clk
s_axis_tvalid
module input wire input wire< DATA_WIDTH-1:0 > input wire s_axis_tvalid
Definition: uart.v:44
txd
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire txd
Definition: uart.v:58
prescale
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire output wire output wire output wire input wire< 15:0 > prescale
Definition: uart.v:73
rst
module input wire rst
Definition: uart.v:38
tx_busy
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire output wire tx_busy
Definition: uart.v:63
s_axis_tready
module input wire input wire< DATA_WIDTH-1:0 > input wire output wire s_axis_tready
Definition: uart.v:45
s_axis_tdata
module input wire input wire< DATA_WIDTH-1:0 > s_axis_tdata
Definition: uart.v:43
busy
module input wire output wire< DATA_WIDTH-1:0 > output wire input wire input wire output wire busy
Definition: uart_rx.v:55

Definition at line 71 of file uart.v.

Referenced by top().

◆ rst

module input wire rst

Definition at line 38 of file uart.v.

Referenced by top().

◆ rx_busy

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire input wire output wire output wire output wire rx_busy

Definition at line 64 of file uart.v.

Referenced by top().

◆ rx_frame_error

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire input wire output wire output wire output wire output wire output wire rx_frame_error

Definition at line 66 of file uart.v.

Referenced by top().

◆ rx_overrun_error

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire input wire output wire output wire output wire output wire rx_overrun_error

Definition at line 65 of file uart.v.

Referenced by top().

◆ rxd

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire input wire rxd

Definition at line 57 of file uart.v.

Referenced by top().

◆ s_axis_tdata

module input wire input wire<DATA_WIDTH-1:0> s_axis_tdata

Definition at line 43 of file uart.v.

Referenced by top().

◆ s_axis_tready

assign s_axis_tready = s_axis_tready_reg

Definition at line 45 of file uart.v.

Referenced by top().

◆ s_axis_tvalid

module input wire input wire<DATA_WIDTH-1:0> input wire s_axis_tvalid

Definition at line 44 of file uart.v.

Referenced by top().

◆ tx_busy

module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire<DATA_WIDTH-1:0> output wire input wire input wire output wire output wire tx_busy

Definition at line 63 of file uart.v.

Referenced by top().

◆ txd

assign txd = txd_reg

Definition at line 58 of file uart.v.

Referenced by top().