5 #(parameter ROW_BITS = 5,
6 parameter COL_BITS = 7)
10 output wire [COL_BITS-1:0] x,
11 output wire [ROW_BITS-1:0] y,
13 input [COL_BITS-1:0] new_x,
14 input [ROW_BITS-1:0] new_y,
26 cursor_x_reg(.clk(clk),
34 cursor_y_reg(.clk(clk),
module simple_register(input wire clk, input wire reset, input wire< SIZE-1:0 > idata, input wire wen, output reg< SIZE-1:0 > odata)
Basic register with synchronous set & reset.
module cursor(input clk, input reset, input tick, output wire< COL_BITS-1:0 > x, output wire< ROW_BITS-1:0 > y, output wire blink_on, input[COL_BITS-1:0] new_x, input[ROW_BITS-1:0] new_y, input wen)
Cursor (position and blinking)
module cursor_blinker(input clk, input reset, input tick, input reset_count, output wire blink_on)
Cursor blinker (uses vblank as tick, blinks about once a second)