vt52-fpga  1.0.0 Initial
vt52-fpga is a serial terminal implemented on a FPGA
char_buffer.v
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1 /**
2  * Char Buffer RAM (1920x8)
3  * (24 lines of 80 characters)
4  */
5 module char_buffer
6  #(parameter BUF_SIZE = 1920,
7  parameter ADDR_BITS = 11)
8  (input wire clk,
9  input wire [7:0] din,
10  input wire [ADDR_BITS-1:0] waddr,
11  input wire wen,
12  input wire [ADDR_BITS-1:0] raddr,
13  output reg [7:0] dout,
14  input wire graphic_mode
15  );
16 
17  reg [7:0] mem [BUF_SIZE-1:0];
18  reg [7:0] atr [BUF_SIZE-1:0];
19 
20  initial begin
21  //$readmemh("mem/test.hex", mem) ;
22  $readmemh("empty.mem", mem) ;
23  end
24 
25  always @(posedge clk) begin
26  if (wen) begin
27  mem[waddr] <= din;
28  atr[waddr] <= graphic_mode;
29  end
30 
31  if((atr[raddr] == 1) && (mem[raddr] > 96) && (mem[raddr] < 128) )
32  dout <= 128 + mem[raddr];
33  else
34  dout <= mem[raddr];
35  end
36 endmodule
module char_buffer(input wire clk, input wire< 7:0 > din, input wire< ADDR_BITS-1:0 > waddr, input wire wen, input wire< ADDR_BITS-1:0 > raddr, output reg< 7:0 > dout, input wire graphic_mode)
Char Buffer RAM (1920x8) (24 lines of 80 characters)
Definition: char_buffer.v:8
always(posedge clk)
Definition: uart_rx.v:86