Go to the source code of this file.
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| module | uart_tx (parameter DATA_WIDTH=8)(input wire clk |
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| | always (posedge clk) |
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| module input wire | rst |
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| module input wire input wire< DATA_WIDTH-1:0 > | s_axis_tdata |
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| module input wire input wire< DATA_WIDTH-1:0 > input wire | s_axis_tvalid |
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| module input wire input wire< DATA_WIDTH-1:0 > input wire output wire | s_axis_tready = s_axis_tready_reg |
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| module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire | txd = txd_reg |
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| module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire output wire | busy = busy_reg |
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| module input wire input wire< DATA_WIDTH-1:0 > input wire output wire output wire output wire input wire< 15:0 > | prescale |
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| reg | txd_reg = 1 |
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| reg | busy_reg = 0 |
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| reg< DATA_WIDTH:0 > | data_reg = 0 |
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| reg< 18:0 > | prescale_reg = 0 |
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| reg< 3:0 > | bit_cnt = 0 |
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◆ always()
◆ bit_cnt
◆ busy
◆ busy_reg
◆ data_reg
| reg<DATA_WIDTH:0> data_reg = 0 |
◆ prescale
| module input wire input wire<DATA_WIDTH-1:0> input wire output wire output wire output wire input wire<15:0> prescale |
Initial value:{
reg s_axis_tready_reg = 0
Definition at line 60 of file uart_tx.v.
Referenced by always().
◆ prescale_reg
| reg<18:0> prescale_reg = 0 |
◆ rst
◆ s_axis_tdata
| module input wire input wire<DATA_WIDTH-1:0> s_axis_tdata |
◆ s_axis_tready
| assign s_axis_tready = s_axis_tready_reg |
◆ s_axis_tvalid
| module input wire input wire<DATA_WIDTH-1:0> input wire s_axis_tvalid |
◆ txd
◆ txd_reg
1.9.1