SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_processing_system7_0_0.h
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1 #ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
2 #define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
3 
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51 
52 
53 #ifndef XTLM
54 #include "xtlm.h"
55 #endif
56 #ifndef SYSTEMC_INCLUDED
57 #include <systemc>
58 #endif
59 
60 #if defined(_MSC_VER)
61 #define DllExport __declspec(dllexport)
62 #elif defined(__GNUC__)
63 #define DllExport __attribute__ ((visibility("default")))
64 #else
65 #define DllExport
66 #endif
67 
68 #include "design_1_processing_system7_0_0_sc.h"
69 
70 
71 
72 
73 #ifdef XILINX_SIMULATOR
74 class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
75 {
76 public:
77 
78  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
79  virtual ~design_1_processing_system7_0_0();
80 
81  // module pin-to-pin RTL interface
82 
83  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_EN;
84  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_ER;
85  sc_core::sc_out< bool > ENET0_MDIO_MDC;
86  sc_core::sc_out< bool > ENET0_MDIO_O;
87  sc_core::sc_out< bool > ENET0_MDIO_T;
88  sc_core::sc_out< sc_dt::sc_bv<8> > ENET0_GMII_TXD;
89  sc_core::sc_in< bool > ENET0_GMII_COL;
90  sc_core::sc_in< bool > ENET0_GMII_CRS;
91  sc_core::sc_in< bool > ENET0_GMII_RX_CLK;
92  sc_core::sc_in< bool > ENET0_GMII_RX_DV;
93  sc_core::sc_in< bool > ENET0_GMII_RX_ER;
94  sc_core::sc_in< bool > ENET0_GMII_TX_CLK;
95  sc_core::sc_in< bool > ENET0_MDIO_I;
96  sc_core::sc_in< bool > ENET0_EXT_INTIN;
97  sc_core::sc_in< sc_dt::sc_bv<8> > ENET0_GMII_RXD;
98  sc_core::sc_in< sc_dt::sc_bv<8> > GPIO_I;
99  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_O;
100  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_T;
101  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
102  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
103  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
104  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
105  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
106  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
107  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
108  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
109  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
110  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
111  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
112  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
113  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
114  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
115  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
116  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
117  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
118  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
119  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
120  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
121  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
122  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
123  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
124  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
125  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
126  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
127  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
128  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
129  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
130  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
131  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
132  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
133  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
134  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
135  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
136  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
137  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
138  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
139  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
140  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
141  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
142  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
143  sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
144  sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
145  sc_core::sc_out< bool > S_AXI_HP0_BVALID;
146  sc_core::sc_out< bool > S_AXI_HP0_RLAST;
147  sc_core::sc_out< bool > S_AXI_HP0_RVALID;
148  sc_core::sc_out< bool > S_AXI_HP0_WREADY;
149  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
150  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
151  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
152  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
153  sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_HP0_RDATA;
154  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
155  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
156  sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
157  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
158  sc_core::sc_in< bool > S_AXI_HP0_ACLK;
159  sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
160  sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
161  sc_core::sc_in< bool > S_AXI_HP0_BREADY;
162  sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
163  sc_core::sc_in< bool > S_AXI_HP0_RREADY;
164  sc_core::sc_in< bool > S_AXI_HP0_WLAST;
165  sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
166  sc_core::sc_in< bool > S_AXI_HP0_WVALID;
167  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
168  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
169  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
170  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
171  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
172  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
173  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
174  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
175  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
176  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
177  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
178  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
179  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
180  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
181  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
182  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
183  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
184  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
185  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
186  sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_HP0_WDATA;
187  sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_HP0_WSTRB;
188  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
189  sc_core::sc_out< bool > FCLK_CLK0;
190  sc_core::sc_out< bool > FCLK_CLK1;
191  sc_core::sc_out< bool > FCLK_CLK2;
192  sc_core::sc_out< bool > FCLK_CLK3;
193  sc_core::sc_out< bool > FCLK_RESET0_N;
194  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
195  sc_core::sc_out< bool > DDR_CAS_n;
196  sc_core::sc_out< bool > DDR_CKE;
197  sc_core::sc_out< bool > DDR_Clk_n;
198  sc_core::sc_out< bool > DDR_Clk;
199  sc_core::sc_out< bool > DDR_CS_n;
200  sc_core::sc_out< bool > DDR_DRSTB;
201  sc_core::sc_out< bool > DDR_ODT;
202  sc_core::sc_out< bool > DDR_RAS_n;
203  sc_core::sc_out< bool > DDR_WEB;
204  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
205  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
206  sc_core::sc_out< bool > DDR_VRN;
207  sc_core::sc_out< bool > DDR_VRP;
208  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
209  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
210  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
211  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
212  sc_core::sc_out< bool > PS_SRSTB;
213  sc_core::sc_out< bool > PS_CLK;
214  sc_core::sc_out< bool > PS_PORB;
215 
216  // Dummy Signals for IP Ports
217 
218 
219 protected:
220 
221  virtual void before_end_of_elaboration();
222 
223 private:
224 
225  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
226  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
227  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
228  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
229  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
230  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
231  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
232  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
233  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
234  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
235  xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
236  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
237  sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
238  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
239  sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
240  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
241  sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
242  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
243  sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
244  sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
245 
246 };
247 #endif // XILINX_SIMULATOR
248 
249 
250 
251 
252 #ifdef XM_SYSTEMC
253 class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
254 {
255 public:
256 
257  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
258  virtual ~design_1_processing_system7_0_0();
259 
260  // module pin-to-pin RTL interface
261 
262  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_EN;
263  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_ER;
264  sc_core::sc_out< bool > ENET0_MDIO_MDC;
265  sc_core::sc_out< bool > ENET0_MDIO_O;
266  sc_core::sc_out< bool > ENET0_MDIO_T;
267  sc_core::sc_out< sc_dt::sc_bv<8> > ENET0_GMII_TXD;
268  sc_core::sc_in< bool > ENET0_GMII_COL;
269  sc_core::sc_in< bool > ENET0_GMII_CRS;
270  sc_core::sc_in< bool > ENET0_GMII_RX_CLK;
271  sc_core::sc_in< bool > ENET0_GMII_RX_DV;
272  sc_core::sc_in< bool > ENET0_GMII_RX_ER;
273  sc_core::sc_in< bool > ENET0_GMII_TX_CLK;
274  sc_core::sc_in< bool > ENET0_MDIO_I;
275  sc_core::sc_in< bool > ENET0_EXT_INTIN;
276  sc_core::sc_in< sc_dt::sc_bv<8> > ENET0_GMII_RXD;
277  sc_core::sc_in< sc_dt::sc_bv<8> > GPIO_I;
278  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_O;
279  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_T;
280  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
281  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
282  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
283  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
284  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
285  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
286  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
287  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
288  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
289  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
290  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
291  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
292  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
293  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
294  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
295  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
296  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
297  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
298  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
299  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
300  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
301  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
302  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
303  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
304  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
305  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
306  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
307  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
308  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
309  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
310  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
311  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
312  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
313  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
314  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
315  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
316  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
317  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
318  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
319  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
320  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
321  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
322  sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
323  sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
324  sc_core::sc_out< bool > S_AXI_HP0_BVALID;
325  sc_core::sc_out< bool > S_AXI_HP0_RLAST;
326  sc_core::sc_out< bool > S_AXI_HP0_RVALID;
327  sc_core::sc_out< bool > S_AXI_HP0_WREADY;
328  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
329  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
330  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
331  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
332  sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_HP0_RDATA;
333  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
334  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
335  sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
336  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
337  sc_core::sc_in< bool > S_AXI_HP0_ACLK;
338  sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
339  sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
340  sc_core::sc_in< bool > S_AXI_HP0_BREADY;
341  sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
342  sc_core::sc_in< bool > S_AXI_HP0_RREADY;
343  sc_core::sc_in< bool > S_AXI_HP0_WLAST;
344  sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
345  sc_core::sc_in< bool > S_AXI_HP0_WVALID;
346  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
347  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
348  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
349  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
350  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
351  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
352  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
353  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
354  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
355  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
356  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
357  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
358  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
359  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
360  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
361  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
362  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
363  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
364  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
365  sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_HP0_WDATA;
366  sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_HP0_WSTRB;
367  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
368  sc_core::sc_out< bool > FCLK_CLK0;
369  sc_core::sc_out< bool > FCLK_CLK1;
370  sc_core::sc_out< bool > FCLK_CLK2;
371  sc_core::sc_out< bool > FCLK_CLK3;
372  sc_core::sc_out< bool > FCLK_RESET0_N;
373  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
374  sc_core::sc_out< bool > DDR_CAS_n;
375  sc_core::sc_out< bool > DDR_CKE;
376  sc_core::sc_out< bool > DDR_Clk_n;
377  sc_core::sc_out< bool > DDR_Clk;
378  sc_core::sc_out< bool > DDR_CS_n;
379  sc_core::sc_out< bool > DDR_DRSTB;
380  sc_core::sc_out< bool > DDR_ODT;
381  sc_core::sc_out< bool > DDR_RAS_n;
382  sc_core::sc_out< bool > DDR_WEB;
383  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
384  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
385  sc_core::sc_out< bool > DDR_VRN;
386  sc_core::sc_out< bool > DDR_VRP;
387  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
388  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
389  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
390  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
391  sc_core::sc_out< bool > PS_SRSTB;
392  sc_core::sc_out< bool > PS_CLK;
393  sc_core::sc_out< bool > PS_PORB;
394 
395  // Dummy Signals for IP Ports
396 
397 
398 protected:
399 
400  virtual void before_end_of_elaboration();
401 
402 private:
403 
404  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
405  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
406  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
407  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
408  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
409  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
410  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
411  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
412  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
413  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
414  xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
415  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
416  sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
417  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
418  sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
419  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
420  sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
421  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
422  sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
423  sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
424 
425 };
426 #endif // XM_SYSTEMC
427 
428 
429 
430 
431 #ifdef RIVIERA
432 class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
433 {
434 public:
435 
436  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
437  virtual ~design_1_processing_system7_0_0();
438 
439  // module pin-to-pin RTL interface
440 
441  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_EN;
442  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_ER;
443  sc_core::sc_out< bool > ENET0_MDIO_MDC;
444  sc_core::sc_out< bool > ENET0_MDIO_O;
445  sc_core::sc_out< bool > ENET0_MDIO_T;
446  sc_core::sc_out< sc_dt::sc_bv<8> > ENET0_GMII_TXD;
447  sc_core::sc_in< bool > ENET0_GMII_COL;
448  sc_core::sc_in< bool > ENET0_GMII_CRS;
449  sc_core::sc_in< bool > ENET0_GMII_RX_CLK;
450  sc_core::sc_in< bool > ENET0_GMII_RX_DV;
451  sc_core::sc_in< bool > ENET0_GMII_RX_ER;
452  sc_core::sc_in< bool > ENET0_GMII_TX_CLK;
453  sc_core::sc_in< bool > ENET0_MDIO_I;
454  sc_core::sc_in< bool > ENET0_EXT_INTIN;
455  sc_core::sc_in< sc_dt::sc_bv<8> > ENET0_GMII_RXD;
456  sc_core::sc_in< sc_dt::sc_bv<8> > GPIO_I;
457  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_O;
458  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_T;
459  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
460  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
461  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
462  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
463  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
464  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
465  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
466  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
467  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
468  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
469  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
470  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
471  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
472  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
473  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
474  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
475  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
476  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
477  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
478  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
479  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
480  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
481  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
482  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
483  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
484  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
485  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
486  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
487  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
488  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
489  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
490  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
491  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
492  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
493  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
494  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
495  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
496  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
497  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
498  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
499  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
500  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
501  sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
502  sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
503  sc_core::sc_out< bool > S_AXI_HP0_BVALID;
504  sc_core::sc_out< bool > S_AXI_HP0_RLAST;
505  sc_core::sc_out< bool > S_AXI_HP0_RVALID;
506  sc_core::sc_out< bool > S_AXI_HP0_WREADY;
507  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
508  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
509  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
510  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
511  sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_HP0_RDATA;
512  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
513  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
514  sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
515  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
516  sc_core::sc_in< bool > S_AXI_HP0_ACLK;
517  sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
518  sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
519  sc_core::sc_in< bool > S_AXI_HP0_BREADY;
520  sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
521  sc_core::sc_in< bool > S_AXI_HP0_RREADY;
522  sc_core::sc_in< bool > S_AXI_HP0_WLAST;
523  sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
524  sc_core::sc_in< bool > S_AXI_HP0_WVALID;
525  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
526  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
527  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
528  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
529  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
530  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
531  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
532  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
533  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
534  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
535  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
536  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
537  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
538  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
539  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
540  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
541  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
542  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
543  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
544  sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_HP0_WDATA;
545  sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_HP0_WSTRB;
546  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
547  sc_core::sc_out< bool > FCLK_CLK0;
548  sc_core::sc_out< bool > FCLK_CLK1;
549  sc_core::sc_out< bool > FCLK_CLK2;
550  sc_core::sc_out< bool > FCLK_CLK3;
551  sc_core::sc_out< bool > FCLK_RESET0_N;
552  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
553  sc_core::sc_out< bool > DDR_CAS_n;
554  sc_core::sc_out< bool > DDR_CKE;
555  sc_core::sc_out< bool > DDR_Clk_n;
556  sc_core::sc_out< bool > DDR_Clk;
557  sc_core::sc_out< bool > DDR_CS_n;
558  sc_core::sc_out< bool > DDR_DRSTB;
559  sc_core::sc_out< bool > DDR_ODT;
560  sc_core::sc_out< bool > DDR_RAS_n;
561  sc_core::sc_out< bool > DDR_WEB;
562  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
563  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
564  sc_core::sc_out< bool > DDR_VRN;
565  sc_core::sc_out< bool > DDR_VRP;
566  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
567  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
568  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
569  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
570  sc_core::sc_out< bool > PS_SRSTB;
571  sc_core::sc_out< bool > PS_CLK;
572  sc_core::sc_out< bool > PS_PORB;
573 
574  // Dummy Signals for IP Ports
575 
576 
577 protected:
578 
579  virtual void before_end_of_elaboration();
580 
581 private:
582 
583  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
584  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
585  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
586  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
587  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
588  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
589  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
590  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
591  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
592  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
593  xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
594  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
595  sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
596  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
597  sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
598  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
599  sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
600  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
601  sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
602  sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
603 
604 };
605 #endif // RIVIERA
606 
607 
608 
609 
610 #ifdef VCSSYSTEMC
611 #include "utils/xtlm_aximm_initiator_stub.h"
612 
613 #include "utils/xtlm_aximm_target_stub.h"
614 
615 class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
616 {
617 public:
618 
619  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
620  virtual ~design_1_processing_system7_0_0();
621 
622  // module pin-to-pin RTL interface
623 
624  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_EN;
625  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_ER;
626  sc_core::sc_out< bool > ENET0_MDIO_MDC;
627  sc_core::sc_out< bool > ENET0_MDIO_O;
628  sc_core::sc_out< bool > ENET0_MDIO_T;
629  sc_core::sc_out< sc_dt::sc_bv<8> > ENET0_GMII_TXD;
630  sc_core::sc_in< bool > ENET0_GMII_COL;
631  sc_core::sc_in< bool > ENET0_GMII_CRS;
632  sc_core::sc_in< bool > ENET0_GMII_RX_CLK;
633  sc_core::sc_in< bool > ENET0_GMII_RX_DV;
634  sc_core::sc_in< bool > ENET0_GMII_RX_ER;
635  sc_core::sc_in< bool > ENET0_GMII_TX_CLK;
636  sc_core::sc_in< bool > ENET0_MDIO_I;
637  sc_core::sc_in< bool > ENET0_EXT_INTIN;
638  sc_core::sc_in< sc_dt::sc_bv<8> > ENET0_GMII_RXD;
639  sc_core::sc_in< sc_dt::sc_bv<8> > GPIO_I;
640  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_O;
641  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_T;
642  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
643  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
644  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
645  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
646  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
647  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
648  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
649  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
650  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
651  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
652  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
653  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
654  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
655  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
656  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
657  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
658  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
659  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
660  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
661  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
662  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
663  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
664  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
665  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
666  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
667  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
668  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
669  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
670  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
671  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
672  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
673  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
674  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
675  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
676  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
677  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
678  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
679  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
680  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
681  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
682  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
683  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
684  sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
685  sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
686  sc_core::sc_out< bool > S_AXI_HP0_BVALID;
687  sc_core::sc_out< bool > S_AXI_HP0_RLAST;
688  sc_core::sc_out< bool > S_AXI_HP0_RVALID;
689  sc_core::sc_out< bool > S_AXI_HP0_WREADY;
690  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
691  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
692  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
693  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
694  sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_HP0_RDATA;
695  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
696  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
697  sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
698  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
699  sc_core::sc_in< bool > S_AXI_HP0_ACLK;
700  sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
701  sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
702  sc_core::sc_in< bool > S_AXI_HP0_BREADY;
703  sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
704  sc_core::sc_in< bool > S_AXI_HP0_RREADY;
705  sc_core::sc_in< bool > S_AXI_HP0_WLAST;
706  sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
707  sc_core::sc_in< bool > S_AXI_HP0_WVALID;
708  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
709  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
710  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
711  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
712  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
713  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
714  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
715  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
716  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
717  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
718  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
719  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
720  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
721  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
722  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
723  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
724  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
725  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
726  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
727  sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_HP0_WDATA;
728  sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_HP0_WSTRB;
729  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
730  sc_core::sc_out< bool > FCLK_CLK0;
731  sc_core::sc_out< bool > FCLK_CLK1;
732  sc_core::sc_out< bool > FCLK_CLK2;
733  sc_core::sc_out< bool > FCLK_CLK3;
734  sc_core::sc_out< bool > FCLK_RESET0_N;
735  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
736  sc_core::sc_out< bool > DDR_CAS_n;
737  sc_core::sc_out< bool > DDR_CKE;
738  sc_core::sc_out< bool > DDR_Clk_n;
739  sc_core::sc_out< bool > DDR_Clk;
740  sc_core::sc_out< bool > DDR_CS_n;
741  sc_core::sc_out< bool > DDR_DRSTB;
742  sc_core::sc_out< bool > DDR_ODT;
743  sc_core::sc_out< bool > DDR_RAS_n;
744  sc_core::sc_out< bool > DDR_WEB;
745  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
746  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
747  sc_core::sc_out< bool > DDR_VRN;
748  sc_core::sc_out< bool > DDR_VRP;
749  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
750  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
751  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
752  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
753  sc_core::sc_out< bool > PS_SRSTB;
754  sc_core::sc_out< bool > PS_CLK;
755  sc_core::sc_out< bool > PS_PORB;
756 
757  // Dummy Signals for IP Ports
758 
759 
760 protected:
761 
762  virtual void before_end_of_elaboration();
763 
764 private:
765 
766  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
767  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
768  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
769  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
770  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
771  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
772  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
773  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
774  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
775  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
776  xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
777  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
778  sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
779  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
780  sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
781  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
782  sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
783  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
784  sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
785  sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
786 
787  // Transactor stubs
788  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
789  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
790  xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_rd_socket_stub;
791  xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_wr_socket_stub;
792 
793  // Socket stubs
794 
795 };
796 #endif // VCSSYSTEMC
797 
798 
799 
800 
801 #ifdef MTI_SYSTEMC
802 #include "utils/xtlm_aximm_initiator_stub.h"
803 
804 #include "utils/xtlm_aximm_target_stub.h"
805 
806 class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
807 {
808 public:
809 
810  design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
811  virtual ~design_1_processing_system7_0_0();
812 
813  // module pin-to-pin RTL interface
814 
815  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_EN;
816  sc_core::sc_out< sc_dt::sc_bv<1> > ENET0_GMII_TX_ER;
817  sc_core::sc_out< bool > ENET0_MDIO_MDC;
818  sc_core::sc_out< bool > ENET0_MDIO_O;
819  sc_core::sc_out< bool > ENET0_MDIO_T;
820  sc_core::sc_out< sc_dt::sc_bv<8> > ENET0_GMII_TXD;
821  sc_core::sc_in< bool > ENET0_GMII_COL;
822  sc_core::sc_in< bool > ENET0_GMII_CRS;
823  sc_core::sc_in< bool > ENET0_GMII_RX_CLK;
824  sc_core::sc_in< bool > ENET0_GMII_RX_DV;
825  sc_core::sc_in< bool > ENET0_GMII_RX_ER;
826  sc_core::sc_in< bool > ENET0_GMII_TX_CLK;
827  sc_core::sc_in< bool > ENET0_MDIO_I;
828  sc_core::sc_in< bool > ENET0_EXT_INTIN;
829  sc_core::sc_in< sc_dt::sc_bv<8> > ENET0_GMII_RXD;
830  sc_core::sc_in< sc_dt::sc_bv<8> > GPIO_I;
831  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_O;
832  sc_core::sc_out< sc_dt::sc_bv<8> > GPIO_T;
833  sc_core::sc_out< bool > TTC0_WAVE0_OUT;
834  sc_core::sc_out< bool > TTC0_WAVE1_OUT;
835  sc_core::sc_out< bool > TTC0_WAVE2_OUT;
836  sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
837  sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
838  sc_core::sc_out< bool > M_AXI_GP0_BREADY;
839  sc_core::sc_out< bool > M_AXI_GP0_RREADY;
840  sc_core::sc_out< bool > M_AXI_GP0_WLAST;
841  sc_core::sc_out< bool > M_AXI_GP0_WVALID;
842  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
843  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
844  sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
845  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
846  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
847  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
848  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
849  sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
850  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
851  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
852  sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
853  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
854  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
855  sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
856  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
857  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
858  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
859  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
860  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
861  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
862  sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
863  sc_core::sc_in< bool > M_AXI_GP0_ACLK;
864  sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
865  sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
866  sc_core::sc_in< bool > M_AXI_GP0_BVALID;
867  sc_core::sc_in< bool > M_AXI_GP0_RLAST;
868  sc_core::sc_in< bool > M_AXI_GP0_RVALID;
869  sc_core::sc_in< bool > M_AXI_GP0_WREADY;
870  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
871  sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
872  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
873  sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
874  sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
875  sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
876  sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
877  sc_core::sc_out< bool > S_AXI_HP0_BVALID;
878  sc_core::sc_out< bool > S_AXI_HP0_RLAST;
879  sc_core::sc_out< bool > S_AXI_HP0_RVALID;
880  sc_core::sc_out< bool > S_AXI_HP0_WREADY;
881  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
882  sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
883  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
884  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
885  sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_HP0_RDATA;
886  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
887  sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
888  sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
889  sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
890  sc_core::sc_in< bool > S_AXI_HP0_ACLK;
891  sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
892  sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
893  sc_core::sc_in< bool > S_AXI_HP0_BREADY;
894  sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
895  sc_core::sc_in< bool > S_AXI_HP0_RREADY;
896  sc_core::sc_in< bool > S_AXI_HP0_WLAST;
897  sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
898  sc_core::sc_in< bool > S_AXI_HP0_WVALID;
899  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
900  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
901  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
902  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
903  sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
904  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
905  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
906  sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
907  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
908  sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
909  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
910  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
911  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
912  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
913  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
914  sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
915  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
916  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
917  sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
918  sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_HP0_WDATA;
919  sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_HP0_WSTRB;
920  sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
921  sc_core::sc_out< bool > FCLK_CLK0;
922  sc_core::sc_out< bool > FCLK_CLK1;
923  sc_core::sc_out< bool > FCLK_CLK2;
924  sc_core::sc_out< bool > FCLK_CLK3;
925  sc_core::sc_out< bool > FCLK_RESET0_N;
926  sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
927  sc_core::sc_out< bool > DDR_CAS_n;
928  sc_core::sc_out< bool > DDR_CKE;
929  sc_core::sc_out< bool > DDR_Clk_n;
930  sc_core::sc_out< bool > DDR_Clk;
931  sc_core::sc_out< bool > DDR_CS_n;
932  sc_core::sc_out< bool > DDR_DRSTB;
933  sc_core::sc_out< bool > DDR_ODT;
934  sc_core::sc_out< bool > DDR_RAS_n;
935  sc_core::sc_out< bool > DDR_WEB;
936  sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
937  sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
938  sc_core::sc_out< bool > DDR_VRN;
939  sc_core::sc_out< bool > DDR_VRP;
940  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
941  sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
942  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
943  sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
944  sc_core::sc_out< bool > PS_SRSTB;
945  sc_core::sc_out< bool > PS_CLK;
946  sc_core::sc_out< bool > PS_PORB;
947 
948  // Dummy Signals for IP Ports
949 
950 
951 protected:
952 
953  virtual void before_end_of_elaboration();
954 
955 private:
956 
957  xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
958  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
959  sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
960  xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
961  sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
962  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
963  sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
964  xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
965  sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
966  sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
967  xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
968  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
969  sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
970  xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
971  sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
972  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
973  sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
974  xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
975  sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
976  sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
977 
978  // Transactor stubs
979  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
980  xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
981  xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_rd_socket_stub;
982  xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_wr_socket_stub;
983 
984  // Socket stubs
985 
986 };
987 #endif // MTI_SYSTEMC
988 #endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
M_AXI_GP0_ARID
bit< 11 :0 > M_AXI_GP0_ARID
Definition: design_1_processing_system7_0_0.sv:179
DDR_DQS_n
bit< 3 :0 > DDR_DQS_n
Definition: design_1_processing_system7_0_0.sv:672
M_AXI_GP0_RVALID
bit M_AXI_GP0_RVALID
Definition: design_1_processing_system7_0_0.sv:205
M_AXI_GP0_WSTRB
bit< 3 :0 > M_AXI_GP0_WSTRB
Definition: design_1_processing_system7_0_0.sv:199
DllExport
#define DllExport
Definition: design_1_processing_system7_0_0.h:65
S_AXI_HP0_AWLEN
bit< 3 :0 > S_AXI_HP0_AWLEN
Definition: design_1_processing_system7_0_0.sv:408
S_AXI_HP0_ARLEN
bit< 3 :0 > S_AXI_HP0_ARLEN
Definition: design_1_processing_system7_0_0.sv:405
S_AXI_HP0_ARPROT
bit< 2 :0 > S_AXI_HP0_ARPROT
Definition: design_1_processing_system7_0_0.sv:400
S_AXI_HP0_BID
bit< 5 :0 > S_AXI_HP0_BID
Definition: design_1_processing_system7_0_0.sv:378
S_AXI_HP0_AWLOCK
bit< 1 :0 > S_AXI_HP0_AWLOCK
Definition: design_1_processing_system7_0_0.sv:398
DDR_VRP
bit DDR_VRP
Definition: design_1_processing_system7_0_0.sv:669
M_AXI_GP0_AWVALID
bit M_AXI_GP0_AWVALID
Definition: design_1_processing_system7_0_0.sv:174
DDR_RAS_n
bit DDR_RAS_n
Definition: design_1_processing_system7_0_0.sv:664
S_AXI_HP0_ARVALID
bit S_AXI_HP0_ARVALID
Definition: design_1_processing_system7_0_0.sv:386
design_1_processing_system7_0_0_sc.h
M_AXI_GP0_AWQOS
bit< 3 :0 > M_AXI_GP0_AWQOS
Definition: design_1_processing_system7_0_0.sv:198
ENET0_MDIO_T
bit ENET0_MDIO_T
Definition: design_1_processing_system7_0_0.sv:13
DDR_CAS_n
bit DDR_CAS_n
Definition: design_1_processing_system7_0_0.sv:657
S_AXI_HP0_WVALID
bit S_AXI_HP0_WVALID
Definition: design_1_processing_system7_0_0.sv:393
S_AXI_HP0_RRESP
bit< 1 :0 > S_AXI_HP0_RRESP
Definition: design_1_processing_system7_0_0.sv:377
S_AXI_HP0_AWREADY
bit S_AXI_HP0_AWREADY
Definition: design_1_processing_system7_0_0.sv:371
DDR_ODT
bit DDR_ODT
Definition: design_1_processing_system7_0_0.sv:663
ENET0_MDIO_O
bit ENET0_MDIO_O
Definition: design_1_processing_system7_0_0.sv:12
M_AXI_GP0_RRESP
bit< 1 :0 > M_AXI_GP0_RRESP
Definition: design_1_processing_system7_0_0.sv:210
M_AXI_GP0_ARLOCK
bit< 1 :0 > M_AXI_GP0_ARLOCK
Definition: design_1_processing_system7_0_0.sv:183
ENET0_GMII_TXD
bit< 7 :0 > ENET0_GMII_TXD
Definition: design_1_processing_system7_0_0.sv:24
design_1_processing_system7_0_0_sc
Definition: design_1_processing_system7_0_0_sc.h:70
S_AXI_HP0_WSTRB
bit< 7 :0 > S_AXI_HP0_WSTRB
Definition: design_1_processing_system7_0_0.sv:414
ENET0_GMII_RXD
bit< 7 :0 > ENET0_GMII_RXD
Definition: design_1_processing_system7_0_0.sv:33
S_AXI_HP0_WLAST
bit S_AXI_HP0_WLAST
Definition: design_1_processing_system7_0_0.sv:391
DDR_VRN
bit DDR_VRN
Definition: design_1_processing_system7_0_0.sv:668
M_AXI_GP0_AWCACHE
bit< 3 :0 > M_AXI_GP0_AWCACHE
Definition: design_1_processing_system7_0_0.sv:196
S_AXI_HP0_AWPROT
bit< 2 :0 > S_AXI_HP0_AWPROT
Definition: design_1_processing_system7_0_0.sv:401
S_AXI_HP0_ARCACHE
bit< 3 :0 > S_AXI_HP0_ARCACHE
Definition: design_1_processing_system7_0_0.sv:404
ENET0_EXT_INTIN
bit ENET0_EXT_INTIN
Definition: design_1_processing_system7_0_0.sv:32
PS_CLK
bit PS_CLK
Definition: design_1_processing_system7_0_0.sv:675
ENET0_GMII_TX_EN
bit< 0 :0 > ENET0_GMII_TX_EN
Definition: design_1_processing_system7_0_0.sv:9
DDR_DM
bit< 3 :0 > DDR_DM
Definition: design_1_processing_system7_0_0.sv:670
ENET0_GMII_RX_ER
bit ENET0_GMII_RX_ER
Definition: design_1_processing_system7_0_0.sv:29
S_AXI_HP0_RACOUNT
bit< 2 :0 > S_AXI_HP0_RACOUNT
Definition: design_1_processing_system7_0_0.sv:383
S_AXI_HP0_RLAST
bit S_AXI_HP0_RLAST
Definition: design_1_processing_system7_0_0.sv:373
S_AXI_HP0_ARSIZE
bit< 2 :0 > S_AXI_HP0_ARSIZE
Definition: design_1_processing_system7_0_0.sv:396
ENET0_MDIO_MDC
bit ENET0_MDIO_MDC
Definition: design_1_processing_system7_0_0.sv:11
S_AXI_HP0_WACOUNT
bit< 5 :0 > S_AXI_HP0_WACOUNT
Definition: design_1_processing_system7_0_0.sv:384
M_AXI_GP0_AWLOCK
bit< 1 :0 > M_AXI_GP0_AWLOCK
Definition: design_1_processing_system7_0_0.sv:186
S_AXI_HP0_ARADDR
bit< 31 :0 > S_AXI_HP0_ARADDR
Definition: design_1_processing_system7_0_0.sv:402
S_AXI_HP0_AWSIZE
bit< 2 :0 > S_AXI_HP0_AWSIZE
Definition: design_1_processing_system7_0_0.sv:399
FCLK_CLK1
bit FCLK_CLK1
Definition: design_1_processing_system7_0_0.sv:617
M_AXI_GP0_AWLEN
bit< 3 :0 > M_AXI_GP0_AWLEN
Definition: design_1_processing_system7_0_0.sv:197
ENET0_GMII_CRS
bit ENET0_GMII_CRS
Definition: design_1_processing_system7_0_0.sv:26
M_AXI_GP0_RDATA
bit< 31 :0 > M_AXI_GP0_RDATA
Definition: design_1_processing_system7_0_0.sv:211
DDR_CKE
bit DDR_CKE
Definition: design_1_processing_system7_0_0.sv:658
S_AXI_HP0_AWVALID
bit S_AXI_HP0_AWVALID
Definition: design_1_processing_system7_0_0.sv:387
S_AXI_HP0_ARBURST
bit< 1 :0 > S_AXI_HP0_ARBURST
Definition: design_1_processing_system7_0_0.sv:394
S_AXI_HP0_ARLOCK
bit< 1 :0 > S_AXI_HP0_ARLOCK
Definition: design_1_processing_system7_0_0.sv:395
FCLK_CLK0
bit FCLK_CLK0
Definition: design_1_processing_system7_0_0.sv:616
FCLK_RESET0_N
bit FCLK_RESET0_N
Definition: design_1_processing_system7_0_0.sv:624
S_AXI_HP0_WREADY
bit S_AXI_HP0_WREADY
Definition: design_1_processing_system7_0_0.sv:375
S_AXI_HP0_ARQOS
bit< 3 :0 > S_AXI_HP0_ARQOS
Definition: design_1_processing_system7_0_0.sv:406
ENET0_GMII_COL
bit ENET0_GMII_COL
Definition: design_1_processing_system7_0_0.sv:25
M_AXI_GP0_AWSIZE
bit< 2 :0 > M_AXI_GP0_AWSIZE
Definition: design_1_processing_system7_0_0.sv:187
M_AXI_GP0_AWADDR
bit< 31 :0 > M_AXI_GP0_AWADDR
Definition: design_1_processing_system7_0_0.sv:191
M_AXI_GP0_AWID
bit< 11 :0 > M_AXI_GP0_AWID
Definition: design_1_processing_system7_0_0.sv:180
S_AXI_HP0_WID
bit< 5 :0 > S_AXI_HP0_WID
Definition: design_1_processing_system7_0_0.sv:412
M_AXI_GP0_ARVALID
bit M_AXI_GP0_ARVALID
Definition: design_1_processing_system7_0_0.sv:173
S_AXI_HP0_RID
bit< 5 :0 > S_AXI_HP0_RID
Definition: design_1_processing_system7_0_0.sv:379
M_AXI_GP0_ARPROT
bit< 2 :0 > M_AXI_GP0_ARPROT
Definition: design_1_processing_system7_0_0.sv:188
S_AXI_HP0_BVALID
bit S_AXI_HP0_BVALID
Definition: design_1_processing_system7_0_0.sv:372
DDR_DQ
bit< 31 :0 > DDR_DQ
Definition: design_1_processing_system7_0_0.sv:671
S_AXI_HP0_AWADDR
bit< 31 :0 > S_AXI_HP0_AWADDR
Definition: design_1_processing_system7_0_0.sv:403
ENET0_GMII_TX_CLK
bit ENET0_GMII_TX_CLK
Definition: design_1_processing_system7_0_0.sv:30
FCLK_CLK3
bit FCLK_CLK3
Definition: design_1_processing_system7_0_0.sv:619
DDR_WEB
bit DDR_WEB
Definition: design_1_processing_system7_0_0.sv:665
M_AXI_GP0_ARQOS
bit< 3 :0 > M_AXI_GP0_ARQOS
Definition: design_1_processing_system7_0_0.sv:195
S_AXI_HP0_RREADY
bit S_AXI_HP0_RREADY
Definition: design_1_processing_system7_0_0.sv:390
M_AXI_GP0_AWREADY
bit M_AXI_GP0_AWREADY
Definition: design_1_processing_system7_0_0.sv:202
IRQ_F2P
bit< 0 :0 > IRQ_F2P
Definition: design_1_processing_system7_0_0.sv:579
PS_SRSTB
bit PS_SRSTB
Definition: design_1_processing_system7_0_0.sv:674
TTC0_WAVE0_OUT
bit TTC0_WAVE0_OUT
Definition: design_1_processing_system7_0_0.sv:148
TTC0_WAVE2_OUT
bit TTC0_WAVE2_OUT
Definition: design_1_processing_system7_0_0.sv:150
M_AXI_GP0_ARADDR
bit< 31 :0 > M_AXI_GP0_ARADDR
Definition: design_1_processing_system7_0_0.sv:190
M_AXI_GP0_ARCACHE
bit< 3 :0 > M_AXI_GP0_ARCACHE
Definition: design_1_processing_system7_0_0.sv:193
design_1_processing_system7_0_0
module design_1_processing_system7_0_0(ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_EXT_INTIN, ENET0_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
Definition: design_1_processing_system7_0_0.sv:679
M_AXI_GP0_WVALID
bit M_AXI_GP0_WVALID
Definition: design_1_processing_system7_0_0.sv:178
ENET0_MDIO_I
bit ENET0_MDIO_I
Definition: design_1_processing_system7_0_0.sv:31
MIO
bit< 53 :0 > MIO
Definition: design_1_processing_system7_0_0.sv:656
GPIO_I
bit< 7 :0 > GPIO_I
Definition: design_1_processing_system7_0_0.sv:59
S_AXI_HP0_RVALID
bit S_AXI_HP0_RVALID
Definition: design_1_processing_system7_0_0.sv:374
ENET0_GMII_RX_DV
bit ENET0_GMII_RX_DV
Definition: design_1_processing_system7_0_0.sv:28
DDR_BankAddr
bit< 2 :0 > DDR_BankAddr
Definition: design_1_processing_system7_0_0.sv:666
PS_PORB
bit PS_PORB
Definition: design_1_processing_system7_0_0.sv:676
GPIO_O
bit< 7 :0 > GPIO_O
Definition: design_1_processing_system7_0_0.sv:60
S_AXI_HP0_WRISSUECAP1_EN
bit S_AXI_HP0_WRISSUECAP1_EN
Definition: design_1_processing_system7_0_0.sv:392
S_AXI_HP0_WDATA
bit< 63 :0 > S_AXI_HP0_WDATA
Definition: design_1_processing_system7_0_0.sv:413
S_AXI_HP0_BREADY
bit S_AXI_HP0_BREADY
Definition: design_1_processing_system7_0_0.sv:388
DDR_DQS
bit< 3 :0 > DDR_DQS
Definition: design_1_processing_system7_0_0.sv:673
S_AXI_HP0_RDISSUECAP1_EN
bit S_AXI_HP0_RDISSUECAP1_EN
Definition: design_1_processing_system7_0_0.sv:389
S_AXI_HP0_RCOUNT
bit< 7 :0 > S_AXI_HP0_RCOUNT
Definition: design_1_processing_system7_0_0.sv:381
M_AXI_GP0_WDATA
bit< 31 :0 > M_AXI_GP0_WDATA
Definition: design_1_processing_system7_0_0.sv:192
S_AXI_HP0_WCOUNT
bit< 7 :0 > S_AXI_HP0_WCOUNT
Definition: design_1_processing_system7_0_0.sv:382
M_AXI_GP0_BID
bit< 11 :0 > M_AXI_GP0_BID
Definition: design_1_processing_system7_0_0.sv:207
S_AXI_HP0_RDATA
bit< 63 :0 > S_AXI_HP0_RDATA
Definition: design_1_processing_system7_0_0.sv:380
M_AXI_GP0_WREADY
bit M_AXI_GP0_WREADY
Definition: design_1_processing_system7_0_0.sv:206
M_AXI_GP0_AWBURST
bit< 1 :0 > M_AXI_GP0_AWBURST
Definition: design_1_processing_system7_0_0.sv:185
M_AXI_GP0_ARREADY
bit M_AXI_GP0_ARREADY
Definition: design_1_processing_system7_0_0.sv:201
M_AXI_GP0_RID
bit< 11 :0 > M_AXI_GP0_RID
Definition: design_1_processing_system7_0_0.sv:208
ENET0_GMII_TX_ER
bit< 0 :0 > ENET0_GMII_TX_ER
Definition: design_1_processing_system7_0_0.sv:10
M_AXI_GP0_AWPROT
bit< 2 :0 > M_AXI_GP0_AWPROT
Definition: design_1_processing_system7_0_0.sv:189
ENET0_GMII_RX_CLK
bit ENET0_GMII_RX_CLK
Definition: design_1_processing_system7_0_0.sv:27
M_AXI_GP0_RREADY
bit M_AXI_GP0_RREADY
Definition: design_1_processing_system7_0_0.sv:176
S_AXI_HP0_ARID
bit< 5 :0 > S_AXI_HP0_ARID
Definition: design_1_processing_system7_0_0.sv:410
DDR_Clk
bit DDR_Clk
Definition: design_1_processing_system7_0_0.sv:660
DDR_Clk_n
bit DDR_Clk_n
Definition: design_1_processing_system7_0_0.sv:659
DDR_Addr
bit< 14 :0 > DDR_Addr
Definition: design_1_processing_system7_0_0.sv:667
M_AXI_GP0_WID
bit< 11 :0 > M_AXI_GP0_WID
Definition: design_1_processing_system7_0_0.sv:181
M_AXI_GP0_BRESP
bit< 1 :0 > M_AXI_GP0_BRESP
Definition: design_1_processing_system7_0_0.sv:209
M_AXI_GP0_RLAST
bit M_AXI_GP0_RLAST
Definition: design_1_processing_system7_0_0.sv:204
M_AXI_GP0_WLAST
bit M_AXI_GP0_WLAST
Definition: design_1_processing_system7_0_0.sv:177
S_AXI_HP0_ACLK
bit S_AXI_HP0_ACLK
Definition: design_1_processing_system7_0_0.sv:385
S_AXI_HP0_AWCACHE
bit< 3 :0 > S_AXI_HP0_AWCACHE
Definition: design_1_processing_system7_0_0.sv:407
M_AXI_GP0_ARBURST
bit< 1 :0 > M_AXI_GP0_ARBURST
Definition: design_1_processing_system7_0_0.sv:182
S_AXI_HP0_BRESP
bit< 1 :0 > S_AXI_HP0_BRESP
Definition: design_1_processing_system7_0_0.sv:376
DDR_DRSTB
bit DDR_DRSTB
Definition: design_1_processing_system7_0_0.sv:662
GPIO_T
bit< 7 :0 > GPIO_T
Definition: design_1_processing_system7_0_0.sv:61
S_AXI_HP0_AWQOS
bit< 3 :0 > S_AXI_HP0_AWQOS
Definition: design_1_processing_system7_0_0.sv:409
FCLK_CLK2
bit FCLK_CLK2
Definition: design_1_processing_system7_0_0.sv:618
S_AXI_HP0_ARREADY
bit S_AXI_HP0_ARREADY
Definition: design_1_processing_system7_0_0.sv:370
M_AXI_GP0_BREADY
bit M_AXI_GP0_BREADY
Definition: design_1_processing_system7_0_0.sv:175
M_AXI_GP0_ARSIZE
bit< 2 :0 > M_AXI_GP0_ARSIZE
Definition: design_1_processing_system7_0_0.sv:184
S_AXI_HP0_AWBURST
bit< 1 :0 > S_AXI_HP0_AWBURST
Definition: design_1_processing_system7_0_0.sv:397
M_AXI_GP0_ACLK
bit M_AXI_GP0_ACLK
Definition: design_1_processing_system7_0_0.sv:200
S_AXI_HP0_AWID
bit< 5 :0 > S_AXI_HP0_AWID
Definition: design_1_processing_system7_0_0.sv:411
DDR_CS_n
bit DDR_CS_n
Definition: design_1_processing_system7_0_0.sv:661
TTC0_WAVE1_OUT
bit TTC0_WAVE1_OUT
Definition: design_1_processing_system7_0_0.sv:149
M_AXI_GP0_ARLEN
bit< 3 :0 > M_AXI_GP0_ARLEN
Definition: design_1_processing_system7_0_0.sv:194
M_AXI_GP0_BVALID
bit M_AXI_GP0_BVALID
Definition: design_1_processing_system7_0_0.sv:203