SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_processing_system7_0_0_sc Class Reference

#include <design_1_processing_system7_0_0_sc.h>

Inheritance diagram for design_1_processing_system7_0_0_sc:
Collaboration diagram for design_1_processing_system7_0_0_sc:

Public Member Functions

 design_1_processing_system7_0_0_sc (const sc_core::sc_module_name &nm)
 
virtual ~design_1_processing_system7_0_0_sc ()
 

Public Attributes

xtlm::xtlm_aximm_initiator_socket * M_AXI_GP0_rd_socket
 
xtlm::xtlm_aximm_initiator_socket * M_AXI_GP0_wr_socket
 
xtlm::xtlm_aximm_target_socket * S_AXI_HP0_rd_socket
 
xtlm::xtlm_aximm_target_socket * S_AXI_HP0_wr_socket
 

Protected Attributes

processing_system7_v5_5_tlmmp_impl
 

Private Member Functions

 design_1_processing_system7_0_0_sc (const design_1_processing_system7_0_0_sc &)
 
const design_1_processing_system7_0_0_scoperator= (const design_1_processing_system7_0_0_sc &)
 

Detailed Description

Definition at line 70 of file design_1_processing_system7_0_0_sc.h.

Constructor & Destructor Documentation

◆ design_1_processing_system7_0_0_sc() [1/2]

◆ ~design_1_processing_system7_0_0_sc()

design_1_processing_system7_0_0_sc::~design_1_processing_system7_0_0_sc ( )
virtual

Definition at line 130 of file design_1_processing_system7_0_0_sc.cpp.

References mp_impl.

◆ design_1_processing_system7_0_0_sc() [2/2]

design_1_processing_system7_0_0_sc::design_1_processing_system7_0_0_sc ( const design_1_processing_system7_0_0_sc )
private

Member Function Documentation

◆ operator=()

const design_1_processing_system7_0_0_sc& design_1_processing_system7_0_0_sc::operator= ( const design_1_processing_system7_0_0_sc )
private

Member Data Documentation

◆ M_AXI_GP0_rd_socket

xtlm::xtlm_aximm_initiator_socket* design_1_processing_system7_0_0_sc::M_AXI_GP0_rd_socket

◆ M_AXI_GP0_wr_socket

xtlm::xtlm_aximm_initiator_socket* design_1_processing_system7_0_0_sc::M_AXI_GP0_wr_socket

◆ mp_impl

processing_system7_v5_5_tlm* design_1_processing_system7_0_0_sc::mp_impl
protected

◆ S_AXI_HP0_rd_socket

xtlm::xtlm_aximm_target_socket* design_1_processing_system7_0_0_sc::S_AXI_HP0_rd_socket

◆ S_AXI_HP0_wr_socket

xtlm::xtlm_aximm_target_socket* design_1_processing_system7_0_0_sc::S_AXI_HP0_wr_socket

The documentation for this class was generated from the following files: