design_1_processing_system7_0_0.sv File Reference

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Functions
module	design_1_processing_system7_0_0 (ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_EXT_INTIN, ENET0_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)

Variables
bit	CAN0_PHY_TX
bit	CAN0_PHY_RX
bit	CAN1_PHY_TX
bit	CAN1_PHY_RX
bit< 0 :0 >	ENET0_GMII_TX_EN
bit< 0 :0 >	ENET0_GMII_TX_ER
bit	ENET0_MDIO_MDC
bit	ENET0_MDIO_O
bit	ENET0_MDIO_T
bit	ENET0_PTP_DELAY_REQ_RX
bit	ENET0_PTP_DELAY_REQ_TX
bit	ENET0_PTP_PDELAY_REQ_RX
bit	ENET0_PTP_PDELAY_REQ_TX
bit	ENET0_PTP_PDELAY_RESP_RX
bit	ENET0_PTP_PDELAY_RESP_TX
bit	ENET0_PTP_SYNC_FRAME_RX
bit	ENET0_PTP_SYNC_FRAME_TX
bit	ENET0_SOF_RX
bit	ENET0_SOF_TX
bit< 7 :0 >	ENET0_GMII_TXD
bit	ENET0_GMII_COL
bit	ENET0_GMII_CRS
bit	ENET0_GMII_RX_CLK
bit	ENET0_GMII_RX_DV
bit	ENET0_GMII_RX_ER
bit	ENET0_GMII_TX_CLK
bit	ENET0_MDIO_I
bit	ENET0_EXT_INTIN
bit< 7 :0 >	ENET0_GMII_RXD
bit< 0 :0 >	ENET1_GMII_TX_EN
bit< 0 :0 >	ENET1_GMII_TX_ER
bit	ENET1_MDIO_MDC
bit	ENET1_MDIO_O
bit	ENET1_MDIO_T
bit	ENET1_PTP_DELAY_REQ_RX
bit	ENET1_PTP_DELAY_REQ_TX
bit	ENET1_PTP_PDELAY_REQ_RX
bit	ENET1_PTP_PDELAY_REQ_TX
bit	ENET1_PTP_PDELAY_RESP_RX
bit	ENET1_PTP_PDELAY_RESP_TX
bit	ENET1_PTP_SYNC_FRAME_RX
bit	ENET1_PTP_SYNC_FRAME_TX
bit	ENET1_SOF_RX
bit	ENET1_SOF_TX
bit< 7 :0 >	ENET1_GMII_TXD
bit	ENET1_GMII_COL
bit	ENET1_GMII_CRS
bit	ENET1_GMII_RX_CLK
bit	ENET1_GMII_RX_DV
bit	ENET1_GMII_RX_ER
bit	ENET1_GMII_TX_CLK
bit	ENET1_MDIO_I
bit	ENET1_EXT_INTIN
bit< 7 :0 >	ENET1_GMII_RXD
bit< 7 :0 >	GPIO_I
bit< 7 :0 >	GPIO_O
bit< 7 :0 >	GPIO_T
bit	I2C0_SDA_I
bit	I2C0_SDA_O
bit	I2C0_SDA_T
bit	I2C0_SCL_I
bit	I2C0_SCL_O
bit	I2C0_SCL_T
bit	I2C1_SDA_I
bit	I2C1_SDA_O
bit	I2C1_SDA_T
bit	I2C1_SCL_I
bit	I2C1_SCL_O
bit	I2C1_SCL_T
bit	PJTAG_TCK
bit	PJTAG_TMS
bit	PJTAG_TDI
bit	PJTAG_TDO
bit	SDIO0_CLK
bit	SDIO0_CLK_FB
bit	SDIO0_CMD_O
bit	SDIO0_CMD_I
bit	SDIO0_CMD_T
bit< 3 :0 >	SDIO0_DATA_I
bit< 3 :0 >	SDIO0_DATA_O
bit< 3 :0 >	SDIO0_DATA_T
bit	SDIO0_LED
bit	SDIO0_CDN
bit	SDIO0_WP
bit	SDIO0_BUSPOW
bit< 2 :0 >	SDIO0_BUSVOLT
bit	SDIO1_CLK
bit	SDIO1_CLK_FB
bit	SDIO1_CMD_O
bit	SDIO1_CMD_I
bit	SDIO1_CMD_T
bit< 3 :0 >	SDIO1_DATA_I
bit< 3 :0 >	SDIO1_DATA_O
bit< 3 :0 >	SDIO1_DATA_T
bit	SDIO1_LED
bit	SDIO1_CDN
bit	SDIO1_WP
bit	SDIO1_BUSPOW
bit< 2 :0 >	SDIO1_BUSVOLT
bit	SPI0_SCLK_I
bit	SPI0_SCLK_O
bit	SPI0_SCLK_T
bit	SPI0_MOSI_I
bit	SPI0_MOSI_O
bit	SPI0_MOSI_T
bit	SPI0_MISO_I
bit	SPI0_MISO_O
bit	SPI0_MISO_T
bit	SPI0_SS_I
bit	SPI0_SS_O
bit	SPI0_SS1_O
bit	SPI0_SS2_O
bit	SPI0_SS_T
bit	SPI1_SCLK_I
bit	SPI1_SCLK_O
bit	SPI1_SCLK_T
bit	SPI1_MOSI_I
bit	SPI1_MOSI_O
bit	SPI1_MOSI_T
bit	SPI1_MISO_I
bit	SPI1_MISO_O
bit	SPI1_MISO_T
bit	SPI1_SS_I
bit	SPI1_SS_O
bit	SPI1_SS1_O
bit	SPI1_SS2_O
bit	SPI1_SS_T
bit	UART0_DTRN
bit	UART0_RTSN
bit	UART0_TX
bit	UART0_CTSN
bit	UART0_DCDN
bit	UART0_DSRN
bit	UART0_RIN
bit	UART0_RX
bit	UART1_DTRN
bit	UART1_RTSN
bit	UART1_TX
bit	UART1_CTSN
bit	UART1_DCDN
bit	UART1_DSRN
bit	UART1_RIN
bit	UART1_RX
bit	TTC0_WAVE0_OUT
bit	TTC0_WAVE1_OUT
bit	TTC0_WAVE2_OUT
bit	TTC0_CLK0_IN
bit	TTC0_CLK1_IN
bit	TTC0_CLK2_IN
bit	TTC1_WAVE0_OUT
bit	TTC1_WAVE1_OUT
bit	TTC1_WAVE2_OUT
bit	TTC1_CLK0_IN
bit	TTC1_CLK1_IN
bit	TTC1_CLK2_IN
bit	WDT_CLK_IN
bit	WDT_RST_OUT
bit	TRACE_CLK
bit	TRACE_CLK_OUT
bit	TRACE_CTL
bit< 1 :0 >	TRACE_DATA
bit< 1 :0 >	USB0_PORT_INDCTL
bit	USB0_VBUS_PWRSELECT
bit	USB0_VBUS_PWRFAULT
bit< 1 :0 >	USB1_PORT_INDCTL
bit	USB1_VBUS_PWRSELECT
bit	USB1_VBUS_PWRFAULT
bit	SRAM_INTIN
bit	M_AXI_GP0_ARVALID
bit	M_AXI_GP0_AWVALID
bit	M_AXI_GP0_BREADY
bit	M_AXI_GP0_RREADY
bit	M_AXI_GP0_WLAST
bit	M_AXI_GP0_WVALID
bit< 11 :0 >	M_AXI_GP0_ARID
bit< 11 :0 >	M_AXI_GP0_AWID
bit< 11 :0 >	M_AXI_GP0_WID
bit< 1 :0 >	M_AXI_GP0_ARBURST
bit< 1 :0 >	M_AXI_GP0_ARLOCK
bit< 2 :0 >	M_AXI_GP0_ARSIZE
bit< 1 :0 >	M_AXI_GP0_AWBURST
bit< 1 :0 >	M_AXI_GP0_AWLOCK
bit< 2 :0 >	M_AXI_GP0_AWSIZE
bit< 2 :0 >	M_AXI_GP0_ARPROT
bit< 2 :0 >	M_AXI_GP0_AWPROT
bit< 31 :0 >	M_AXI_GP0_ARADDR
bit< 31 :0 >	M_AXI_GP0_AWADDR
bit< 31 :0 >	M_AXI_GP0_WDATA
bit< 3 :0 >	M_AXI_GP0_ARCACHE
bit< 3 :0 >	M_AXI_GP0_ARLEN
bit< 3 :0 >	M_AXI_GP0_ARQOS
bit< 3 :0 >	M_AXI_GP0_AWCACHE
bit< 3 :0 >	M_AXI_GP0_AWLEN
bit< 3 :0 >	M_AXI_GP0_AWQOS
bit< 3 :0 >	M_AXI_GP0_WSTRB
bit	M_AXI_GP0_ACLK
bit	M_AXI_GP0_ARREADY
bit	M_AXI_GP0_AWREADY
bit	M_AXI_GP0_BVALID
bit	M_AXI_GP0_RLAST
bit	M_AXI_GP0_RVALID
bit	M_AXI_GP0_WREADY
bit< 11 :0 >	M_AXI_GP0_BID
bit< 11 :0 >	M_AXI_GP0_RID
bit< 1 :0 >	M_AXI_GP0_BRESP
bit< 1 :0 >	M_AXI_GP0_RRESP
bit< 31 :0 >	M_AXI_GP0_RDATA
bit	M_AXI_GP1_ARVALID
bit	M_AXI_GP1_AWVALID
bit	M_AXI_GP1_BREADY
bit	M_AXI_GP1_RREADY
bit	M_AXI_GP1_WLAST
bit	M_AXI_GP1_WVALID
bit< 11 :0 >	M_AXI_GP1_ARID
bit< 11 :0 >	M_AXI_GP1_AWID
bit< 11 :0 >	M_AXI_GP1_WID
bit< 1 :0 >	M_AXI_GP1_ARBURST
bit< 1 :0 >	M_AXI_GP1_ARLOCK
bit< 2 :0 >	M_AXI_GP1_ARSIZE
bit< 1 :0 >	M_AXI_GP1_AWBURST
bit< 1 :0 >	M_AXI_GP1_AWLOCK
bit< 2 :0 >	M_AXI_GP1_AWSIZE
bit< 2 :0 >	M_AXI_GP1_ARPROT
bit< 2 :0 >	M_AXI_GP1_AWPROT
bit< 31 :0 >	M_AXI_GP1_ARADDR
bit< 31 :0 >	M_AXI_GP1_AWADDR
bit< 31 :0 >	M_AXI_GP1_WDATA
bit< 3 :0 >	M_AXI_GP1_ARCACHE
bit< 3 :0 >	M_AXI_GP1_ARLEN
bit< 3 :0 >	M_AXI_GP1_ARQOS
bit< 3 :0 >	M_AXI_GP1_AWCACHE
bit< 3 :0 >	M_AXI_GP1_AWLEN
bit< 3 :0 >	M_AXI_GP1_AWQOS
bit< 3 :0 >	M_AXI_GP1_WSTRB
bit	M_AXI_GP1_ACLK
bit	M_AXI_GP1_ARREADY
bit	M_AXI_GP1_AWREADY
bit	M_AXI_GP1_BVALID
bit	M_AXI_GP1_RLAST
bit	M_AXI_GP1_RVALID
bit	M_AXI_GP1_WREADY
bit< 11 :0 >	M_AXI_GP1_BID
bit< 11 :0 >	M_AXI_GP1_RID
bit< 1 :0 >	M_AXI_GP1_BRESP
bit< 1 :0 >	M_AXI_GP1_RRESP
bit< 31 :0 >	M_AXI_GP1_RDATA
bit	S_AXI_GP0_ARREADY
bit	S_AXI_GP0_AWREADY
bit	S_AXI_GP0_BVALID
bit	S_AXI_GP0_RLAST
bit	S_AXI_GP0_RVALID
bit	S_AXI_GP0_WREADY
bit< 1 :0 >	S_AXI_GP0_BRESP
bit< 1 :0 >	S_AXI_GP0_RRESP
bit< 31 :0 >	S_AXI_GP0_RDATA
bit< 5 :0 >	S_AXI_GP0_BID
bit< 5 :0 >	S_AXI_GP0_RID
bit	S_AXI_GP0_ACLK
bit	S_AXI_GP0_ARVALID
bit	S_AXI_GP0_AWVALID
bit	S_AXI_GP0_BREADY
bit	S_AXI_GP0_RREADY
bit	S_AXI_GP0_WLAST
bit	S_AXI_GP0_WVALID
bit< 1 :0 >	S_AXI_GP0_ARBURST
bit< 1 :0 >	S_AXI_GP0_ARLOCK
bit< 2 :0 >	S_AXI_GP0_ARSIZE
bit< 1 :0 >	S_AXI_GP0_AWBURST
bit< 1 :0 >	S_AXI_GP0_AWLOCK
bit< 2 :0 >	S_AXI_GP0_AWSIZE
bit< 2 :0 >	S_AXI_GP0_ARPROT
bit< 2 :0 >	S_AXI_GP0_AWPROT
bit< 31 :0 >	S_AXI_GP0_ARADDR
bit< 31 :0 >	S_AXI_GP0_AWADDR
bit< 31 :0 >	S_AXI_GP0_WDATA
bit< 3 :0 >	S_AXI_GP0_ARCACHE
bit< 3 :0 >	S_AXI_GP0_ARLEN
bit< 3 :0 >	S_AXI_GP0_ARQOS
bit< 3 :0 >	S_AXI_GP0_AWCACHE
bit< 3 :0 >	S_AXI_GP0_AWLEN
bit< 3 :0 >	S_AXI_GP0_AWQOS
bit< 3 :0 >	S_AXI_GP0_WSTRB
bit< 5 :0 >	S_AXI_GP0_ARID
bit< 5 :0 >	S_AXI_GP0_AWID
bit< 5 :0 >	S_AXI_GP0_WID
bit	S_AXI_GP1_ARREADY
bit	S_AXI_GP1_AWREADY
bit	S_AXI_GP1_BVALID
bit	S_AXI_GP1_RLAST
bit	S_AXI_GP1_RVALID
bit	S_AXI_GP1_WREADY
bit< 1 :0 >	S_AXI_GP1_BRESP
bit< 1 :0 >	S_AXI_GP1_RRESP
bit< 31 :0 >	S_AXI_GP1_RDATA
bit< 5 :0 >	S_AXI_GP1_BID
bit< 5 :0 >	S_AXI_GP1_RID
bit	S_AXI_GP1_ACLK
bit	S_AXI_GP1_ARVALID
bit	S_AXI_GP1_AWVALID
bit	S_AXI_GP1_BREADY
bit	S_AXI_GP1_RREADY
bit	S_AXI_GP1_WLAST
bit	S_AXI_GP1_WVALID
bit< 1 :0 >	S_AXI_GP1_ARBURST
bit< 1 :0 >	S_AXI_GP1_ARLOCK
bit< 2 :0 >	S_AXI_GP1_ARSIZE
bit< 1 :0 >	S_AXI_GP1_AWBURST
bit< 1 :0 >	S_AXI_GP1_AWLOCK
bit< 2 :0 >	S_AXI_GP1_AWSIZE
bit< 2 :0 >	S_AXI_GP1_ARPROT
bit< 2 :0 >	S_AXI_GP1_AWPROT
bit< 31 :0 >	S_AXI_GP1_ARADDR
bit< 31 :0 >	S_AXI_GP1_AWADDR
bit< 31 :0 >	S_AXI_GP1_WDATA
bit< 3 :0 >	S_AXI_GP1_ARCACHE
bit< 3 :0 >	S_AXI_GP1_ARLEN
bit< 3 :0 >	S_AXI_GP1_ARQOS
bit< 3 :0 >	S_AXI_GP1_AWCACHE
bit< 3 :0 >	S_AXI_GP1_AWLEN
bit< 3 :0 >	S_AXI_GP1_AWQOS
bit< 3 :0 >	S_AXI_GP1_WSTRB
bit< 5 :0 >	S_AXI_GP1_ARID
bit< 5 :0 >	S_AXI_GP1_AWID
bit< 5 :0 >	S_AXI_GP1_WID
bit	S_AXI_ACP_ARREADY
bit	S_AXI_ACP_AWREADY
bit	S_AXI_ACP_BVALID
bit	S_AXI_ACP_RLAST
bit	S_AXI_ACP_RVALID
bit	S_AXI_ACP_WREADY
bit< 1 :0 >	S_AXI_ACP_BRESP
bit< 1 :0 >	S_AXI_ACP_RRESP
bit< 2 :0 >	S_AXI_ACP_BID
bit< 2 :0 >	S_AXI_ACP_RID
bit< 63 :0 >	S_AXI_ACP_RDATA
bit	S_AXI_ACP_ACLK
bit	S_AXI_ACP_ARVALID
bit	S_AXI_ACP_AWVALID
bit	S_AXI_ACP_BREADY
bit	S_AXI_ACP_RREADY
bit	S_AXI_ACP_WLAST
bit	S_AXI_ACP_WVALID
bit< 2 :0 >	S_AXI_ACP_ARID
bit< 2 :0 >	S_AXI_ACP_ARPROT
bit< 2 :0 >	S_AXI_ACP_AWID
bit< 2 :0 >	S_AXI_ACP_AWPROT
bit< 2 :0 >	S_AXI_ACP_WID
bit< 31 :0 >	S_AXI_ACP_ARADDR
bit< 31 :0 >	S_AXI_ACP_AWADDR
bit< 3 :0 >	S_AXI_ACP_ARCACHE
bit< 3 :0 >	S_AXI_ACP_ARLEN
bit< 3 :0 >	S_AXI_ACP_ARQOS
bit< 3 :0 >	S_AXI_ACP_AWCACHE
bit< 3 :0 >	S_AXI_ACP_AWLEN
bit< 3 :0 >	S_AXI_ACP_AWQOS
bit< 1 :0 >	S_AXI_ACP_ARBURST
bit< 1 :0 >	S_AXI_ACP_ARLOCK
bit< 2 :0 >	S_AXI_ACP_ARSIZE
bit< 1 :0 >	S_AXI_ACP_AWBURST
bit< 1 :0 >	S_AXI_ACP_AWLOCK
bit< 2 :0 >	S_AXI_ACP_AWSIZE
bit< 4 :0 >	S_AXI_ACP_ARUSER
bit< 4 :0 >	S_AXI_ACP_AWUSER
bit< 63 :0 >	S_AXI_ACP_WDATA
bit< 7 :0 >	S_AXI_ACP_WSTRB
bit	S_AXI_HP0_ARREADY
bit	S_AXI_HP0_AWREADY
bit	S_AXI_HP0_BVALID
bit	S_AXI_HP0_RLAST
bit	S_AXI_HP0_RVALID
bit	S_AXI_HP0_WREADY
bit< 1 :0 >	S_AXI_HP0_BRESP
bit< 1 :0 >	S_AXI_HP0_RRESP
bit< 5 :0 >	S_AXI_HP0_BID
bit< 5 :0 >	S_AXI_HP0_RID
bit< 63 :0 >	S_AXI_HP0_RDATA
bit< 7 :0 >	S_AXI_HP0_RCOUNT
bit< 7 :0 >	S_AXI_HP0_WCOUNT
bit< 2 :0 >	S_AXI_HP0_RACOUNT
bit< 5 :0 >	S_AXI_HP0_WACOUNT
bit	S_AXI_HP0_ACLK
bit	S_AXI_HP0_ARVALID
bit	S_AXI_HP0_AWVALID
bit	S_AXI_HP0_BREADY
bit	S_AXI_HP0_RDISSUECAP1_EN
bit	S_AXI_HP0_RREADY
bit	S_AXI_HP0_WLAST
bit	S_AXI_HP0_WRISSUECAP1_EN
bit	S_AXI_HP0_WVALID
bit< 1 :0 >	S_AXI_HP0_ARBURST
bit< 1 :0 >	S_AXI_HP0_ARLOCK
bit< 2 :0 >	S_AXI_HP0_ARSIZE
bit< 1 :0 >	S_AXI_HP0_AWBURST
bit< 1 :0 >	S_AXI_HP0_AWLOCK
bit< 2 :0 >	S_AXI_HP0_AWSIZE
bit< 2 :0 >	S_AXI_HP0_ARPROT
bit< 2 :0 >	S_AXI_HP0_AWPROT
bit< 31 :0 >	S_AXI_HP0_ARADDR
bit< 31 :0 >	S_AXI_HP0_AWADDR
bit< 3 :0 >	S_AXI_HP0_ARCACHE
bit< 3 :0 >	S_AXI_HP0_ARLEN
bit< 3 :0 >	S_AXI_HP0_ARQOS
bit< 3 :0 >	S_AXI_HP0_AWCACHE
bit< 3 :0 >	S_AXI_HP0_AWLEN
bit< 3 :0 >	S_AXI_HP0_AWQOS
bit< 5 :0 >	S_AXI_HP0_ARID
bit< 5 :0 >	S_AXI_HP0_AWID
bit< 5 :0 >	S_AXI_HP0_WID
bit< 63 :0 >	S_AXI_HP0_WDATA
bit< 7 :0 >	S_AXI_HP0_WSTRB
bit	S_AXI_HP1_ARREADY
bit	S_AXI_HP1_AWREADY
bit	S_AXI_HP1_BVALID
bit	S_AXI_HP1_RLAST
bit	S_AXI_HP1_RVALID
bit	S_AXI_HP1_WREADY
bit< 1 :0 >	S_AXI_HP1_BRESP
bit< 1 :0 >	S_AXI_HP1_RRESP
bit< 5 :0 >	S_AXI_HP1_BID
bit< 5 :0 >	S_AXI_HP1_RID
bit< 63 :0 >	S_AXI_HP1_RDATA
bit< 7 :0 >	S_AXI_HP1_RCOUNT
bit< 7 :0 >	S_AXI_HP1_WCOUNT
bit< 2 :0 >	S_AXI_HP1_RACOUNT
bit< 5 :0 >	S_AXI_HP1_WACOUNT
bit	S_AXI_HP1_ACLK
bit	S_AXI_HP1_ARVALID
bit	S_AXI_HP1_AWVALID
bit	S_AXI_HP1_BREADY
bit	S_AXI_HP1_RDISSUECAP1_EN
bit	S_AXI_HP1_RREADY
bit	S_AXI_HP1_WLAST
bit	S_AXI_HP1_WRISSUECAP1_EN
bit	S_AXI_HP1_WVALID
bit< 1 :0 >	S_AXI_HP1_ARBURST
bit< 1 :0 >	S_AXI_HP1_ARLOCK
bit< 2 :0 >	S_AXI_HP1_ARSIZE
bit< 1 :0 >	S_AXI_HP1_AWBURST
bit< 1 :0 >	S_AXI_HP1_AWLOCK
bit< 2 :0 >	S_AXI_HP1_AWSIZE
bit< 2 :0 >	S_AXI_HP1_ARPROT
bit< 2 :0 >	S_AXI_HP1_AWPROT
bit< 31 :0 >	S_AXI_HP1_ARADDR
bit< 31 :0 >	S_AXI_HP1_AWADDR
bit< 3 :0 >	S_AXI_HP1_ARCACHE
bit< 3 :0 >	S_AXI_HP1_ARLEN
bit< 3 :0 >	S_AXI_HP1_ARQOS
bit< 3 :0 >	S_AXI_HP1_AWCACHE
bit< 3 :0 >	S_AXI_HP1_AWLEN
bit< 3 :0 >	S_AXI_HP1_AWQOS
bit< 5 :0 >	S_AXI_HP1_ARID
bit< 5 :0 >	S_AXI_HP1_AWID
bit< 5 :0 >	S_AXI_HP1_WID
bit< 63 :0 >	S_AXI_HP1_WDATA
bit< 7 :0 >	S_AXI_HP1_WSTRB
bit	S_AXI_HP2_ARREADY
bit	S_AXI_HP2_AWREADY
bit	S_AXI_HP2_BVALID
bit	S_AXI_HP2_RLAST
bit	S_AXI_HP2_RVALID
bit	S_AXI_HP2_WREADY
bit< 1 :0 >	S_AXI_HP2_BRESP
bit< 1 :0 >	S_AXI_HP2_RRESP
bit< 5 :0 >	S_AXI_HP2_BID
bit< 5 :0 >	S_AXI_HP2_RID
bit< 63 :0 >	S_AXI_HP2_RDATA
bit< 7 :0 >	S_AXI_HP2_RCOUNT
bit< 7 :0 >	S_AXI_HP2_WCOUNT
bit< 2 :0 >	S_AXI_HP2_RACOUNT
bit< 5 :0 >	S_AXI_HP2_WACOUNT
bit	S_AXI_HP2_ACLK
bit	S_AXI_HP2_ARVALID
bit	S_AXI_HP2_AWVALID
bit	S_AXI_HP2_BREADY
bit	S_AXI_HP2_RDISSUECAP1_EN
bit	S_AXI_HP2_RREADY
bit	S_AXI_HP2_WLAST
bit	S_AXI_HP2_WRISSUECAP1_EN
bit	S_AXI_HP2_WVALID
bit< 1 :0 >	S_AXI_HP2_ARBURST
bit< 1 :0 >	S_AXI_HP2_ARLOCK
bit< 2 :0 >	S_AXI_HP2_ARSIZE
bit< 1 :0 >	S_AXI_HP2_AWBURST
bit< 1 :0 >	S_AXI_HP2_AWLOCK
bit< 2 :0 >	S_AXI_HP2_AWSIZE
bit< 2 :0 >	S_AXI_HP2_ARPROT
bit< 2 :0 >	S_AXI_HP2_AWPROT
bit< 31 :0 >	S_AXI_HP2_ARADDR
bit< 31 :0 >	S_AXI_HP2_AWADDR
bit< 3 :0 >	S_AXI_HP2_ARCACHE
bit< 3 :0 >	S_AXI_HP2_ARLEN
bit< 3 :0 >	S_AXI_HP2_ARQOS
bit< 3 :0 >	S_AXI_HP2_AWCACHE
bit< 3 :0 >	S_AXI_HP2_AWLEN
bit< 3 :0 >	S_AXI_HP2_AWQOS
bit< 5 :0 >	S_AXI_HP2_ARID
bit< 5 :0 >	S_AXI_HP2_AWID
bit< 5 :0 >	S_AXI_HP2_WID
bit< 63 :0 >	S_AXI_HP2_WDATA
bit< 7 :0 >	S_AXI_HP2_WSTRB
bit	S_AXI_HP3_ARREADY
bit	S_AXI_HP3_AWREADY
bit	S_AXI_HP3_BVALID
bit	S_AXI_HP3_RLAST
bit	S_AXI_HP3_RVALID
bit	S_AXI_HP3_WREADY
bit< 1 :0 >	S_AXI_HP3_BRESP
bit< 1 :0 >	S_AXI_HP3_RRESP
bit< 5 :0 >	S_AXI_HP3_BID
bit< 5 :0 >	S_AXI_HP3_RID
bit< 63 :0 >	S_AXI_HP3_RDATA
bit< 7 :0 >	S_AXI_HP3_RCOUNT
bit< 7 :0 >	S_AXI_HP3_WCOUNT
bit< 2 :0 >	S_AXI_HP3_RACOUNT
bit< 5 :0 >	S_AXI_HP3_WACOUNT
bit	S_AXI_HP3_ACLK
bit	S_AXI_HP3_ARVALID
bit	S_AXI_HP3_AWVALID
bit	S_AXI_HP3_BREADY
bit	S_AXI_HP3_RDISSUECAP1_EN
bit	S_AXI_HP3_RREADY
bit	S_AXI_HP3_WLAST
bit	S_AXI_HP3_WRISSUECAP1_EN
bit	S_AXI_HP3_WVALID
bit< 1 :0 >	S_AXI_HP3_ARBURST
bit< 1 :0 >	S_AXI_HP3_ARLOCK
bit< 2 :0 >	S_AXI_HP3_ARSIZE
bit< 1 :0 >	S_AXI_HP3_AWBURST
bit< 1 :0 >	S_AXI_HP3_AWLOCK
bit< 2 :0 >	S_AXI_HP3_AWSIZE
bit< 2 :0 >	S_AXI_HP3_ARPROT
bit< 2 :0 >	S_AXI_HP3_AWPROT
bit< 31 :0 >	S_AXI_HP3_ARADDR
bit< 31 :0 >	S_AXI_HP3_AWADDR
bit< 3 :0 >	S_AXI_HP3_ARCACHE
bit< 3 :0 >	S_AXI_HP3_ARLEN
bit< 3 :0 >	S_AXI_HP3_ARQOS
bit< 3 :0 >	S_AXI_HP3_AWCACHE
bit< 3 :0 >	S_AXI_HP3_AWLEN
bit< 3 :0 >	S_AXI_HP3_AWQOS
bit< 5 :0 >	S_AXI_HP3_ARID
bit< 5 :0 >	S_AXI_HP3_AWID
bit< 5 :0 >	S_AXI_HP3_WID
bit< 63 :0 >	S_AXI_HP3_WDATA
bit< 7 :0 >	S_AXI_HP3_WSTRB
bit	IRQ_P2F_DMAC_ABORT
bit	IRQ_P2F_DMAC0
bit	IRQ_P2F_DMAC1
bit	IRQ_P2F_DMAC2
bit	IRQ_P2F_DMAC3
bit	IRQ_P2F_DMAC4
bit	IRQ_P2F_DMAC5
bit	IRQ_P2F_DMAC6
bit	IRQ_P2F_DMAC7
bit	IRQ_P2F_SMC
bit	IRQ_P2F_QSPI
bit	IRQ_P2F_CTI
bit	IRQ_P2F_GPIO
bit	IRQ_P2F_USB0
bit	IRQ_P2F_ENET0
bit	IRQ_P2F_ENET_WAKE0
bit	IRQ_P2F_SDIO0
bit	IRQ_P2F_I2C0
bit	IRQ_P2F_SPI0
bit	IRQ_P2F_UART0
bit	IRQ_P2F_CAN0
bit	IRQ_P2F_USB1
bit	IRQ_P2F_ENET1
bit	IRQ_P2F_ENET_WAKE1
bit	IRQ_P2F_SDIO1
bit	IRQ_P2F_I2C1
bit	IRQ_P2F_SPI1
bit	IRQ_P2F_UART1
bit	IRQ_P2F_CAN1
bit< 0 :0 >	IRQ_F2P
bit	Core0_nFIQ
bit	Core0_nIRQ
bit	Core1_nFIQ
bit	Core1_nIRQ
bit< 1 :0 >	DMA0_DATYPE
bit	DMA0_DAVALID
bit	DMA0_DRREADY
bit< 1 :0 >	DMA1_DATYPE
bit	DMA1_DAVALID
bit	DMA1_DRREADY
bit< 1 :0 >	DMA2_DATYPE
bit	DMA2_DAVALID
bit	DMA2_DRREADY
bit< 1 :0 >	DMA3_DATYPE
bit	DMA3_DAVALID
bit	DMA3_DRREADY
bit	DMA0_ACLK
bit	DMA0_DAREADY
bit	DMA0_DRLAST
bit	DMA0_DRVALID
bit	DMA1_ACLK
bit	DMA1_DAREADY
bit	DMA1_DRLAST
bit	DMA1_DRVALID
bit	DMA2_ACLK
bit	DMA2_DAREADY
bit	DMA2_DRLAST
bit	DMA2_DRVALID
bit	DMA3_ACLK
bit	DMA3_DAREADY
bit	DMA3_DRLAST
bit	DMA3_DRVALID
bit< 1 :0 >	DMA0_DRTYPE
bit< 1 :0 >	DMA1_DRTYPE
bit< 1 :0 >	DMA2_DRTYPE
bit< 1 :0 >	DMA3_DRTYPE
bit	FCLK_CLK0
bit	FCLK_CLK1
bit	FCLK_CLK2
bit	FCLK_CLK3
bit	FCLK_CLKTRIG0_N
bit	FCLK_CLKTRIG1_N
bit	FCLK_CLKTRIG2_N
bit	FCLK_CLKTRIG3_N
bit	FCLK_RESET0_N
bit	FCLK_RESET1_N
bit	FCLK_RESET2_N
bit	FCLK_RESET3_N
bit< 31 :0 >	FTMD_TRACEIN_DATA
bit	FTMD_TRACEIN_VALID
bit	FTMD_TRACEIN_CLK
bit< 3 :0 >	FTMD_TRACEIN_ATID
bit	FTMT_F2P_TRIG_0
bit	FTMT_F2P_TRIGACK_0
bit	FTMT_F2P_TRIG_1
bit	FTMT_F2P_TRIGACK_1
bit	FTMT_F2P_TRIG_2
bit	FTMT_F2P_TRIGACK_2
bit	FTMT_F2P_TRIG_3
bit	FTMT_F2P_TRIGACK_3
bit< 31 :0 >	FTMT_F2P_DEBUG
bit	FTMT_P2F_TRIGACK_0
bit	FTMT_P2F_TRIG_0
bit	FTMT_P2F_TRIGACK_1
bit	FTMT_P2F_TRIG_1
bit	FTMT_P2F_TRIGACK_2
bit	FTMT_P2F_TRIG_2
bit	FTMT_P2F_TRIGACK_3
bit	FTMT_P2F_TRIG_3
bit< 31 :0 >	FTMT_P2F_DEBUG
bit	FPGA_IDLE_N
bit	EVENT_EVENTO
bit< 1 :0 >	EVENT_STANDBYWFE
bit< 1 :0 >	EVENT_STANDBYWFI
bit	EVENT_EVENTI
bit< 3 :0 >	DDR_ARB
bit< 53 :0 >	MIO
bit	DDR_CAS_n
bit	DDR_CKE
bit	DDR_Clk_n
bit	DDR_Clk
bit	DDR_CS_n
bit	DDR_DRSTB
bit	DDR_ODT
bit	DDR_RAS_n
bit	DDR_WEB
bit< 2 :0 >	DDR_BankAddr
bit< 14 :0 >	DDR_Addr
bit	DDR_VRN
bit	DDR_VRP
bit< 3 :0 >	DDR_DM
bit< 31 :0 >	DDR_DQ
bit< 3 :0 >	DDR_DQS_n
bit< 3 :0 >	DDR_DQS
bit	PS_SRSTB
bit	PS_CLK
bit	PS_PORB

Variable Documentation

CAN0_PHY_RX

bit CAN0_PHY_RX

Definition at line 6 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

CAN0_PHY_TX

bit CAN0_PHY_TX

Definition at line 5 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

CAN1_PHY_RX

bit CAN1_PHY_RX

Definition at line 8 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

CAN1_PHY_TX

bit CAN1_PHY_TX

Definition at line 7 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

Core0_nFIQ

bit Core0_nFIQ

Definition at line 580 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

Core0_nIRQ

bit Core0_nIRQ

Definition at line 581 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

Core1_nFIQ

bit Core1_nFIQ

Definition at line 582 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

Core1_nIRQ

bit Core1_nIRQ

Definition at line 583 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DDR_Addr

bit<14 : 0> DDR_Addr

Definition at line 667 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_ARB

bit<3 : 0> DDR_ARB

Definition at line 655 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DDR_BankAddr

bit<2 : 0> DDR_BankAddr

Definition at line 666 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_CAS_n

bit DDR_CAS_n

Definition at line 657 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_CKE

bit DDR_CKE

Definition at line 658 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_Clk

bit DDR_Clk

Definition at line 660 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_Clk_n

bit DDR_Clk_n

Definition at line 659 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_CS_n

bit DDR_CS_n

Definition at line 661 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_DM

bit<3 : 0> DDR_DM

Definition at line 670 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_DQ

bit<31 : 0> DDR_DQ

Definition at line 671 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_DQS

bit<3 : 0> DDR_DQS

Definition at line 673 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_DQS_n

bit<3 : 0> DDR_DQS_n

Definition at line 672 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_DRSTB

bit DDR_DRSTB

Definition at line 662 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_ODT

bit DDR_ODT

Definition at line 663 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_RAS_n

bit DDR_RAS_n

Definition at line 664 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_VRN

bit DDR_VRN

Definition at line 668 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_VRP

bit DDR_VRP

Definition at line 669 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DDR_WEB

bit DDR_WEB

Definition at line 665 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

DMA0_ACLK

bit DMA0_ACLK

Definition at line 596 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DAREADY

bit DMA0_DAREADY

Definition at line 597 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DATYPE

bit<1 : 0> DMA0_DATYPE

Definition at line 584 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DAVALID

bit DMA0_DAVALID

Definition at line 585 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DRLAST

bit DMA0_DRLAST

Definition at line 598 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DRREADY

bit DMA0_DRREADY

Definition at line 586 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DRTYPE

bit<1 : 0> DMA0_DRTYPE

Definition at line 612 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA0_DRVALID

bit DMA0_DRVALID

Definition at line 599 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_ACLK

bit DMA1_ACLK

Definition at line 600 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DAREADY

bit DMA1_DAREADY

Definition at line 601 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DATYPE

bit<1 : 0> DMA1_DATYPE

Definition at line 587 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DAVALID

bit DMA1_DAVALID

Definition at line 588 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DRLAST

bit DMA1_DRLAST

Definition at line 602 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DRREADY

bit DMA1_DRREADY

Definition at line 589 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DRTYPE

bit<1 : 0> DMA1_DRTYPE

Definition at line 613 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA1_DRVALID

bit DMA1_DRVALID

Definition at line 603 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_ACLK

bit DMA2_ACLK

Definition at line 604 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DAREADY

bit DMA2_DAREADY

Definition at line 605 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DATYPE

bit<1 : 0> DMA2_DATYPE

Definition at line 590 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DAVALID

bit DMA2_DAVALID

Definition at line 591 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DRLAST

bit DMA2_DRLAST

Definition at line 606 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DRREADY

bit DMA2_DRREADY

Definition at line 592 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DRTYPE

bit<1 : 0> DMA2_DRTYPE

Definition at line 614 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA2_DRVALID

bit DMA2_DRVALID

Definition at line 607 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_ACLK

bit DMA3_ACLK

Definition at line 608 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DAREADY

bit DMA3_DAREADY

Definition at line 609 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DATYPE

bit<1 : 0> DMA3_DATYPE

Definition at line 593 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DAVALID

bit DMA3_DAVALID

Definition at line 594 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DRLAST

bit DMA3_DRLAST

Definition at line 610 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DRREADY

bit DMA3_DRREADY

Definition at line 595 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DRTYPE

bit<1 : 0> DMA3_DRTYPE

Definition at line 615 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

DMA3_DRVALID

bit DMA3_DRVALID

Definition at line 611 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_EXT_INTIN

bit ENET0_EXT_INTIN

Definition at line 32 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_COL

bit ENET0_GMII_COL

Definition at line 25 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_CRS

bit ENET0_GMII_CRS

Definition at line 26 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_RX_CLK

bit ENET0_GMII_RX_CLK

Definition at line 27 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_RX_DV

bit ENET0_GMII_RX_DV

Definition at line 28 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_RX_ER

bit ENET0_GMII_RX_ER

Definition at line 29 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_RXD

bit<7 : 0> ENET0_GMII_RXD

Definition at line 33 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_TX_CLK

bit ENET0_GMII_TX_CLK

Definition at line 30 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_TX_EN

bit<0 : 0> ENET0_GMII_TX_EN

Definition at line 9 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_TX_ER

bit<0 : 0> ENET0_GMII_TX_ER

Definition at line 10 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_GMII_TXD

bit<7 : 0> ENET0_GMII_TXD

Definition at line 24 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_MDIO_I

bit ENET0_MDIO_I

Definition at line 31 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_MDIO_MDC

bit ENET0_MDIO_MDC

Definition at line 11 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_MDIO_O

bit ENET0_MDIO_O

Definition at line 12 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_MDIO_T

bit ENET0_MDIO_T

Definition at line 13 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

ENET0_PTP_DELAY_REQ_RX

bit ENET0_PTP_DELAY_REQ_RX

Definition at line 14 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_DELAY_REQ_TX

bit ENET0_PTP_DELAY_REQ_TX

Definition at line 15 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_PDELAY_REQ_RX

bit ENET0_PTP_PDELAY_REQ_RX

Definition at line 16 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_PDELAY_REQ_TX

bit ENET0_PTP_PDELAY_REQ_TX

Definition at line 17 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_PDELAY_RESP_RX

bit ENET0_PTP_PDELAY_RESP_RX

Definition at line 18 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_PDELAY_RESP_TX

bit ENET0_PTP_PDELAY_RESP_TX

Definition at line 19 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_SYNC_FRAME_RX

bit ENET0_PTP_SYNC_FRAME_RX

Definition at line 20 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_PTP_SYNC_FRAME_TX

bit ENET0_PTP_SYNC_FRAME_TX

Definition at line 21 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_SOF_RX

bit ENET0_SOF_RX

Definition at line 22 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET0_SOF_TX

bit ENET0_SOF_TX

Definition at line 23 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_EXT_INTIN

bit ENET1_EXT_INTIN

Definition at line 57 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_COL

bit ENET1_GMII_COL

Definition at line 50 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_CRS

bit ENET1_GMII_CRS

Definition at line 51 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_RX_CLK

bit ENET1_GMII_RX_CLK

Definition at line 52 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_RX_DV

bit ENET1_GMII_RX_DV

Definition at line 53 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_RX_ER

bit ENET1_GMII_RX_ER

Definition at line 54 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_RXD

bit<7 : 0> ENET1_GMII_RXD

Definition at line 58 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_TX_CLK

bit ENET1_GMII_TX_CLK

Definition at line 55 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_TX_EN

bit<0 : 0> ENET1_GMII_TX_EN

Definition at line 34 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_TX_ER

bit<0 : 0> ENET1_GMII_TX_ER

Definition at line 35 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_GMII_TXD

bit<7 : 0> ENET1_GMII_TXD

Definition at line 49 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_MDIO_I

bit ENET1_MDIO_I

Definition at line 56 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_MDIO_MDC

bit ENET1_MDIO_MDC

Definition at line 36 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_MDIO_O

bit ENET1_MDIO_O

Definition at line 37 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_MDIO_T

bit ENET1_MDIO_T

Definition at line 38 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_DELAY_REQ_RX

bit ENET1_PTP_DELAY_REQ_RX

Definition at line 39 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_DELAY_REQ_TX

bit ENET1_PTP_DELAY_REQ_TX

Definition at line 40 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_PDELAY_REQ_RX

bit ENET1_PTP_PDELAY_REQ_RX

Definition at line 41 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_PDELAY_REQ_TX

bit ENET1_PTP_PDELAY_REQ_TX

Definition at line 42 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_PDELAY_RESP_RX

bit ENET1_PTP_PDELAY_RESP_RX

Definition at line 43 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_PDELAY_RESP_TX

bit ENET1_PTP_PDELAY_RESP_TX

Definition at line 44 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_SYNC_FRAME_RX

bit ENET1_PTP_SYNC_FRAME_RX

Definition at line 45 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_PTP_SYNC_FRAME_TX

bit ENET1_PTP_SYNC_FRAME_TX

Definition at line 46 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_SOF_RX

bit ENET1_SOF_RX

Definition at line 47 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

ENET1_SOF_TX

bit ENET1_SOF_TX

Definition at line 48 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

EVENT_EVENTI

bit EVENT_EVENTI

Definition at line 654 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

EVENT_EVENTO

bit EVENT_EVENTO

Definition at line 651 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

EVENT_STANDBYWFE

bit<1 : 0> EVENT_STANDBYWFE

Definition at line 652 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

EVENT_STANDBYWFI

bit<1 : 0> EVENT_STANDBYWFI

Definition at line 653 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FCLK_CLK0

bit FCLK_CLK0

Definition at line 616 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_CLK1

bit FCLK_CLK1

Definition at line 617 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_CLK2

bit FCLK_CLK2

Definition at line 618 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_CLK3

bit FCLK_CLK3

Definition at line 619 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_CLKTRIG0_N

bit FCLK_CLKTRIG0_N

Definition at line 620 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FCLK_CLKTRIG1_N

bit FCLK_CLKTRIG1_N

Definition at line 621 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FCLK_CLKTRIG2_N

bit FCLK_CLKTRIG2_N

Definition at line 622 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FCLK_CLKTRIG3_N

bit FCLK_CLKTRIG3_N

Definition at line 623 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FCLK_RESET0_N

bit FCLK_RESET0_N

Definition at line 624 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_RESET1_N

bit FCLK_RESET1_N

Definition at line 625 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_RESET2_N

bit FCLK_RESET2_N

Definition at line 626 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FCLK_RESET3_N

bit FCLK_RESET3_N

Definition at line 627 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

FPGA_IDLE_N

bit FPGA_IDLE_N

Definition at line 650 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMD_TRACEIN_ATID

bit<3 : 0> FTMD_TRACEIN_ATID

Definition at line 631 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMD_TRACEIN_CLK

bit FTMD_TRACEIN_CLK

Definition at line 630 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMD_TRACEIN_DATA

bit<31 : 0> FTMD_TRACEIN_DATA

Definition at line 628 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMD_TRACEIN_VALID

bit FTMD_TRACEIN_VALID

Definition at line 629 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMT_F2P_DEBUG

bit<31 : 0> FTMT_F2P_DEBUG

Definition at line 640 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMT_F2P_TRIG_0

bit FTMT_F2P_TRIG_0

Definition at line 632 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIG_1

bit FTMT_F2P_TRIG_1

Definition at line 634 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIG_2

bit FTMT_F2P_TRIG_2

Definition at line 636 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIG_3

bit FTMT_F2P_TRIG_3

Definition at line 638 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIGACK_0

bit FTMT_F2P_TRIGACK_0

Definition at line 633 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIGACK_1

bit FTMT_F2P_TRIGACK_1

Definition at line 635 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIGACK_2

bit FTMT_F2P_TRIGACK_2

Definition at line 637 of file design_1_processing_system7_0_0.sv.

FTMT_F2P_TRIGACK_3

bit FTMT_F2P_TRIGACK_3

Definition at line 639 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_DEBUG

bit<31 : 0> FTMT_P2F_DEBUG

Definition at line 649 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

FTMT_P2F_TRIG_0

bit FTMT_P2F_TRIG_0

Definition at line 642 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIG_1

bit FTMT_P2F_TRIG_1

Definition at line 644 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIG_2

bit FTMT_P2F_TRIG_2

Definition at line 646 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIG_3

bit FTMT_P2F_TRIG_3

Definition at line 648 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIGACK_0

bit FTMT_P2F_TRIGACK_0

Definition at line 641 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIGACK_1

bit FTMT_P2F_TRIGACK_1

Definition at line 643 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIGACK_2

bit FTMT_P2F_TRIGACK_2

Definition at line 645 of file design_1_processing_system7_0_0.sv.

FTMT_P2F_TRIGACK_3

bit FTMT_P2F_TRIGACK_3

Definition at line 647 of file design_1_processing_system7_0_0.sv.

GPIO_I

bit<7 : 0> GPIO_I

Definition at line 59 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

GPIO_O

bit<7 : 0> GPIO_O

Definition at line 60 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

GPIO_T

bit<7 : 0> GPIO_T

Definition at line 61 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

I2C0_SCL_I

bit I2C0_SCL_I

Definition at line 65 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C0_SCL_O

bit I2C0_SCL_O

Definition at line 66 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C0_SCL_T

bit I2C0_SCL_T

Definition at line 67 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C0_SDA_I

bit I2C0_SDA_I

Definition at line 62 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C0_SDA_O

bit I2C0_SDA_O

Definition at line 63 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C0_SDA_T

bit I2C0_SDA_T

Definition at line 64 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C1_SCL_I

bit I2C1_SCL_I

Definition at line 71 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C1_SCL_O

bit I2C1_SCL_O

Definition at line 72 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C1_SCL_T

bit I2C1_SCL_T

Definition at line 73 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C1_SDA_I

bit I2C1_SDA_I

Definition at line 68 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C1_SDA_O

bit I2C1_SDA_O

Definition at line 69 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

I2C1_SDA_T

bit I2C1_SDA_T

Definition at line 70 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_F2P

bit<0 : 0> IRQ_F2P

Definition at line 579 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

IRQ_P2F_CAN0

bit IRQ_P2F_CAN0

Definition at line 570 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_CAN1

bit IRQ_P2F_CAN1

Definition at line 578 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_CTI

bit IRQ_P2F_CTI

Definition at line 561 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC0

bit IRQ_P2F_DMAC0

Definition at line 551 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC1

bit IRQ_P2F_DMAC1

Definition at line 552 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC2

bit IRQ_P2F_DMAC2

Definition at line 553 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC3

bit IRQ_P2F_DMAC3

Definition at line 554 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC4

bit IRQ_P2F_DMAC4

Definition at line 555 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC5

bit IRQ_P2F_DMAC5

Definition at line 556 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC6

bit IRQ_P2F_DMAC6

Definition at line 557 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC7

bit IRQ_P2F_DMAC7

Definition at line 558 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_DMAC_ABORT

bit IRQ_P2F_DMAC_ABORT

Definition at line 550 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_ENET0

bit IRQ_P2F_ENET0

Definition at line 564 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_ENET1

bit IRQ_P2F_ENET1

Definition at line 572 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_ENET_WAKE0

bit IRQ_P2F_ENET_WAKE0

Definition at line 565 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_ENET_WAKE1

bit IRQ_P2F_ENET_WAKE1

Definition at line 573 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_GPIO

bit IRQ_P2F_GPIO

Definition at line 562 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_I2C0

bit IRQ_P2F_I2C0

Definition at line 567 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_I2C1

bit IRQ_P2F_I2C1

Definition at line 575 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_QSPI

bit IRQ_P2F_QSPI

Definition at line 560 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_SDIO0

bit IRQ_P2F_SDIO0

Definition at line 566 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_SDIO1

bit IRQ_P2F_SDIO1

Definition at line 574 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_SMC

bit IRQ_P2F_SMC

Definition at line 559 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_SPI0

bit IRQ_P2F_SPI0

Definition at line 568 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_SPI1

bit IRQ_P2F_SPI1

Definition at line 576 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_UART0

bit IRQ_P2F_UART0

Definition at line 569 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_UART1

bit IRQ_P2F_UART1

Definition at line 577 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_USB0

bit IRQ_P2F_USB0

Definition at line 563 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

IRQ_P2F_USB1

bit IRQ_P2F_USB1

Definition at line 571 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP0_ACLK

bit M_AXI_GP0_ACLK

Definition at line 200 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARADDR

bit<31 : 0> M_AXI_GP0_ARADDR

Definition at line 190 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARBURST

bit<1 : 0> M_AXI_GP0_ARBURST

Definition at line 182 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARCACHE

bit<3 : 0> M_AXI_GP0_ARCACHE

Definition at line 193 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARID

bit<11 : 0> M_AXI_GP0_ARID

Definition at line 179 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARLEN

bit<3 : 0> M_AXI_GP0_ARLEN

Definition at line 194 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARLOCK

bit<1 : 0> M_AXI_GP0_ARLOCK

Definition at line 183 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARPROT

bit<2 : 0> M_AXI_GP0_ARPROT

Definition at line 188 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARQOS

bit<3 : 0> M_AXI_GP0_ARQOS

Definition at line 195 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARREADY

bit M_AXI_GP0_ARREADY

Definition at line 201 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARSIZE

bit<2 : 0> M_AXI_GP0_ARSIZE

Definition at line 184 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_ARVALID

bit M_AXI_GP0_ARVALID

Definition at line 173 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWADDR

bit<31 : 0> M_AXI_GP0_AWADDR

Definition at line 191 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWBURST

bit<1 : 0> M_AXI_GP0_AWBURST

Definition at line 185 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWCACHE

bit<3 : 0> M_AXI_GP0_AWCACHE

Definition at line 196 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWID

bit<11 : 0> M_AXI_GP0_AWID

Definition at line 180 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWLEN

bit<3 : 0> M_AXI_GP0_AWLEN

Definition at line 197 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWLOCK

bit<1 : 0> M_AXI_GP0_AWLOCK

Definition at line 186 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWPROT

bit<2 : 0> M_AXI_GP0_AWPROT

Definition at line 189 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWQOS

bit<3 : 0> M_AXI_GP0_AWQOS

Definition at line 198 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWREADY

bit M_AXI_GP0_AWREADY

Definition at line 202 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWSIZE

bit<2 : 0> M_AXI_GP0_AWSIZE

Definition at line 187 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_AWVALID

bit M_AXI_GP0_AWVALID

Definition at line 174 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_BID

bit<11 : 0> M_AXI_GP0_BID

Definition at line 207 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_BREADY

bit M_AXI_GP0_BREADY

Definition at line 175 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_BRESP

bit<1 : 0> M_AXI_GP0_BRESP

Definition at line 209 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_BVALID

bit M_AXI_GP0_BVALID

Definition at line 203 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_RDATA

bit<31 : 0> M_AXI_GP0_RDATA

Definition at line 211 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_RID

bit<11 : 0> M_AXI_GP0_RID

Definition at line 208 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_RLAST

bit M_AXI_GP0_RLAST

Definition at line 204 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_RREADY

bit M_AXI_GP0_RREADY

Definition at line 176 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_RRESP

bit<1 : 0> M_AXI_GP0_RRESP

Definition at line 210 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_RVALID

bit M_AXI_GP0_RVALID

Definition at line 205 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_WDATA

bit<31 : 0> M_AXI_GP0_WDATA

Definition at line 192 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_WID

bit<11 : 0> M_AXI_GP0_WID

Definition at line 181 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_WLAST

bit M_AXI_GP0_WLAST

Definition at line 177 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_WREADY

bit M_AXI_GP0_WREADY

Definition at line 206 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_WSTRB

bit<3 : 0> M_AXI_GP0_WSTRB

Definition at line 199 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP0_WVALID

bit M_AXI_GP0_WVALID

Definition at line 178 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

M_AXI_GP1_ACLK

bit M_AXI_GP1_ACLK

Definition at line 239 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARADDR

bit<31 : 0> M_AXI_GP1_ARADDR

Definition at line 229 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARBURST

bit<1 : 0> M_AXI_GP1_ARBURST

Definition at line 221 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARCACHE

bit<3 : 0> M_AXI_GP1_ARCACHE

Definition at line 232 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARID

bit<11 : 0> M_AXI_GP1_ARID

Definition at line 218 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARLEN

bit<3 : 0> M_AXI_GP1_ARLEN

Definition at line 233 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARLOCK

bit<1 : 0> M_AXI_GP1_ARLOCK

Definition at line 222 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARPROT

bit<2 : 0> M_AXI_GP1_ARPROT

Definition at line 227 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARQOS

bit<3 : 0> M_AXI_GP1_ARQOS

Definition at line 234 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARREADY

bit M_AXI_GP1_ARREADY

Definition at line 240 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARSIZE

bit<2 : 0> M_AXI_GP1_ARSIZE

Definition at line 223 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_ARVALID

bit M_AXI_GP1_ARVALID

Definition at line 212 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWADDR

bit<31 : 0> M_AXI_GP1_AWADDR

Definition at line 230 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWBURST

bit<1 : 0> M_AXI_GP1_AWBURST

Definition at line 224 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWCACHE

bit<3 : 0> M_AXI_GP1_AWCACHE

Definition at line 235 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWID

bit<11 : 0> M_AXI_GP1_AWID

Definition at line 219 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWLEN

bit<3 : 0> M_AXI_GP1_AWLEN

Definition at line 236 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWLOCK

bit<1 : 0> M_AXI_GP1_AWLOCK

Definition at line 225 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWPROT

bit<2 : 0> M_AXI_GP1_AWPROT

Definition at line 228 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWQOS

bit<3 : 0> M_AXI_GP1_AWQOS

Definition at line 237 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWREADY

bit M_AXI_GP1_AWREADY

Definition at line 241 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWSIZE

bit<2 : 0> M_AXI_GP1_AWSIZE

Definition at line 226 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_AWVALID

bit M_AXI_GP1_AWVALID

Definition at line 213 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_BID

bit<11 : 0> M_AXI_GP1_BID

Definition at line 246 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_BREADY

bit M_AXI_GP1_BREADY

Definition at line 214 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_BRESP

bit<1 : 0> M_AXI_GP1_BRESP

Definition at line 248 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_BVALID

bit M_AXI_GP1_BVALID

Definition at line 242 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_RDATA

bit<31 : 0> M_AXI_GP1_RDATA

Definition at line 250 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_RID

bit<11 : 0> M_AXI_GP1_RID

Definition at line 247 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_RLAST

bit M_AXI_GP1_RLAST

Definition at line 243 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_RREADY

bit M_AXI_GP1_RREADY

Definition at line 215 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_RRESP

bit<1 : 0> M_AXI_GP1_RRESP

Definition at line 249 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_RVALID

bit M_AXI_GP1_RVALID

Definition at line 244 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_WDATA

bit<31 : 0> M_AXI_GP1_WDATA

Definition at line 231 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_WID

bit<11 : 0> M_AXI_GP1_WID

Definition at line 220 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_WLAST

bit M_AXI_GP1_WLAST

Definition at line 216 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_WREADY

bit M_AXI_GP1_WREADY

Definition at line 245 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_WSTRB

bit<3 : 0> M_AXI_GP1_WSTRB

Definition at line 238 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

M_AXI_GP1_WVALID

bit M_AXI_GP1_WVALID

Definition at line 217 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

MIO

bit<53 : 0> MIO

Definition at line 656 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

PJTAG_TCK

bit PJTAG_TCK

Definition at line 74 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

PJTAG_TDI

bit PJTAG_TDI

Definition at line 76 of file design_1_processing_system7_0_0.sv.

PJTAG_TDO

bit PJTAG_TDO

Definition at line 77 of file design_1_processing_system7_0_0.sv.

PJTAG_TMS

bit PJTAG_TMS

Definition at line 75 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

PS_CLK

bit PS_CLK

Definition at line 675 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

PS_PORB

bit PS_PORB

Definition at line 676 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

PS_SRSTB

bit PS_SRSTB

Definition at line 674 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_ACP_ACLK

bit S_AXI_ACP_ACLK

Definition at line 340 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARADDR

bit<31 : 0> S_AXI_ACP_ARADDR

Definition at line 352 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARBURST

bit<1 : 0> S_AXI_ACP_ARBURST

Definition at line 360 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARCACHE

bit<3 : 0> S_AXI_ACP_ARCACHE

Definition at line 354 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARID

bit<2 : 0> S_AXI_ACP_ARID

Definition at line 347 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARLEN

bit<3 : 0> S_AXI_ACP_ARLEN

Definition at line 355 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARLOCK

bit<1 : 0> S_AXI_ACP_ARLOCK

Definition at line 361 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARPROT

bit<2 : 0> S_AXI_ACP_ARPROT

Definition at line 348 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARQOS

bit<3 : 0> S_AXI_ACP_ARQOS

Definition at line 356 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARREADY

bit S_AXI_ACP_ARREADY

Definition at line 329 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARSIZE

bit<2 : 0> S_AXI_ACP_ARSIZE

Definition at line 362 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARUSER

bit<4 : 0> S_AXI_ACP_ARUSER

Definition at line 366 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_ARVALID

bit S_AXI_ACP_ARVALID

Definition at line 341 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWADDR

bit<31 : 0> S_AXI_ACP_AWADDR

Definition at line 353 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWBURST

bit<1 : 0> S_AXI_ACP_AWBURST

Definition at line 363 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWCACHE

bit<3 : 0> S_AXI_ACP_AWCACHE

Definition at line 357 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWID

bit<2 : 0> S_AXI_ACP_AWID

Definition at line 349 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWLEN

bit<3 : 0> S_AXI_ACP_AWLEN

Definition at line 358 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWLOCK

bit<1 : 0> S_AXI_ACP_AWLOCK

Definition at line 364 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWPROT

bit<2 : 0> S_AXI_ACP_AWPROT

Definition at line 350 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWQOS

bit<3 : 0> S_AXI_ACP_AWQOS

Definition at line 359 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWREADY

bit S_AXI_ACP_AWREADY

Definition at line 330 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWSIZE

bit<2 : 0> S_AXI_ACP_AWSIZE

Definition at line 365 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWUSER

bit<4 : 0> S_AXI_ACP_AWUSER

Definition at line 367 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_AWVALID

bit S_AXI_ACP_AWVALID

Definition at line 342 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_BID

bit<2 : 0> S_AXI_ACP_BID

Definition at line 337 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_BREADY

bit S_AXI_ACP_BREADY

Definition at line 343 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_BRESP

bit<1 : 0> S_AXI_ACP_BRESP

Definition at line 335 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_BVALID

bit S_AXI_ACP_BVALID

Definition at line 331 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_RDATA

bit<63 : 0> S_AXI_ACP_RDATA

Definition at line 339 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_RID

bit<2 : 0> S_AXI_ACP_RID

Definition at line 338 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_RLAST

bit S_AXI_ACP_RLAST

Definition at line 332 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_RREADY

bit S_AXI_ACP_RREADY

Definition at line 344 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_RRESP

bit<1 : 0> S_AXI_ACP_RRESP

Definition at line 336 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_RVALID

bit S_AXI_ACP_RVALID

Definition at line 333 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_WDATA

bit<63 : 0> S_AXI_ACP_WDATA

Definition at line 368 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_WID

bit<2 : 0> S_AXI_ACP_WID

Definition at line 351 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_WLAST

bit S_AXI_ACP_WLAST

Definition at line 345 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_WREADY

bit S_AXI_ACP_WREADY

Definition at line 334 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_WSTRB

bit<7 : 0> S_AXI_ACP_WSTRB

Definition at line 369 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_ACP_WVALID

bit S_AXI_ACP_WVALID

Definition at line 346 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ACLK

bit S_AXI_GP0_ACLK

Definition at line 262 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARADDR

bit<31 : 0> S_AXI_GP0_ARADDR

Definition at line 277 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARBURST

bit<1 : 0> S_AXI_GP0_ARBURST

Definition at line 269 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARCACHE

bit<3 : 0> S_AXI_GP0_ARCACHE

Definition at line 280 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARID

bit<5 : 0> S_AXI_GP0_ARID

Definition at line 287 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARLEN

bit<3 : 0> S_AXI_GP0_ARLEN

Definition at line 281 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARLOCK

bit<1 : 0> S_AXI_GP0_ARLOCK

Definition at line 270 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARPROT

bit<2 : 0> S_AXI_GP0_ARPROT

Definition at line 275 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARQOS

bit<3 : 0> S_AXI_GP0_ARQOS

Definition at line 282 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARREADY

bit S_AXI_GP0_ARREADY

Definition at line 251 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARSIZE

bit<2 : 0> S_AXI_GP0_ARSIZE

Definition at line 271 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_ARVALID

bit S_AXI_GP0_ARVALID

Definition at line 263 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWADDR

bit<31 : 0> S_AXI_GP0_AWADDR

Definition at line 278 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWBURST

bit<1 : 0> S_AXI_GP0_AWBURST

Definition at line 272 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWCACHE

bit<3 : 0> S_AXI_GP0_AWCACHE

Definition at line 283 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWID

bit<5 : 0> S_AXI_GP0_AWID

Definition at line 288 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWLEN

bit<3 : 0> S_AXI_GP0_AWLEN

Definition at line 284 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWLOCK

bit<1 : 0> S_AXI_GP0_AWLOCK

Definition at line 273 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWPROT

bit<2 : 0> S_AXI_GP0_AWPROT

Definition at line 276 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWQOS

bit<3 : 0> S_AXI_GP0_AWQOS

Definition at line 285 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWREADY

bit S_AXI_GP0_AWREADY

Definition at line 252 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWSIZE

bit<2 : 0> S_AXI_GP0_AWSIZE

Definition at line 274 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_AWVALID

bit S_AXI_GP0_AWVALID

Definition at line 264 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_BID

bit<5 : 0> S_AXI_GP0_BID

Definition at line 260 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_BREADY

bit S_AXI_GP0_BREADY

Definition at line 265 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_BRESP

bit<1 : 0> S_AXI_GP0_BRESP

Definition at line 257 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_BVALID

bit S_AXI_GP0_BVALID

Definition at line 253 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_RDATA

bit<31 : 0> S_AXI_GP0_RDATA

Definition at line 259 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_RID

bit<5 : 0> S_AXI_GP0_RID

Definition at line 261 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_RLAST

bit S_AXI_GP0_RLAST

Definition at line 254 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_RREADY

bit S_AXI_GP0_RREADY

Definition at line 266 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_RRESP

bit<1 : 0> S_AXI_GP0_RRESP

Definition at line 258 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_RVALID

bit S_AXI_GP0_RVALID

Definition at line 255 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_WDATA

bit<31 : 0> S_AXI_GP0_WDATA

Definition at line 279 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_WID

bit<5 : 0> S_AXI_GP0_WID

Definition at line 289 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_WLAST

bit S_AXI_GP0_WLAST

Definition at line 267 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_WREADY

bit S_AXI_GP0_WREADY

Definition at line 256 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_WSTRB

bit<3 : 0> S_AXI_GP0_WSTRB

Definition at line 286 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP0_WVALID

bit S_AXI_GP0_WVALID

Definition at line 268 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ACLK

bit S_AXI_GP1_ACLK

Definition at line 301 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARADDR

bit<31 : 0> S_AXI_GP1_ARADDR

Definition at line 316 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARBURST

bit<1 : 0> S_AXI_GP1_ARBURST

Definition at line 308 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARCACHE

bit<3 : 0> S_AXI_GP1_ARCACHE

Definition at line 319 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARID

bit<5 : 0> S_AXI_GP1_ARID

Definition at line 326 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARLEN

bit<3 : 0> S_AXI_GP1_ARLEN

Definition at line 320 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARLOCK

bit<1 : 0> S_AXI_GP1_ARLOCK

Definition at line 309 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARPROT

bit<2 : 0> S_AXI_GP1_ARPROT

Definition at line 314 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARQOS

bit<3 : 0> S_AXI_GP1_ARQOS

Definition at line 321 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARREADY

bit S_AXI_GP1_ARREADY

Definition at line 290 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARSIZE

bit<2 : 0> S_AXI_GP1_ARSIZE

Definition at line 310 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_ARVALID

bit S_AXI_GP1_ARVALID

Definition at line 302 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWADDR

bit<31 : 0> S_AXI_GP1_AWADDR

Definition at line 317 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWBURST

bit<1 : 0> S_AXI_GP1_AWBURST

Definition at line 311 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWCACHE

bit<3 : 0> S_AXI_GP1_AWCACHE

Definition at line 322 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWID

bit<5 : 0> S_AXI_GP1_AWID

Definition at line 327 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWLEN

bit<3 : 0> S_AXI_GP1_AWLEN

Definition at line 323 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWLOCK

bit<1 : 0> S_AXI_GP1_AWLOCK

Definition at line 312 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWPROT

bit<2 : 0> S_AXI_GP1_AWPROT

Definition at line 315 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWQOS

bit<3 : 0> S_AXI_GP1_AWQOS

Definition at line 324 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWREADY

bit S_AXI_GP1_AWREADY

Definition at line 291 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWSIZE

bit<2 : 0> S_AXI_GP1_AWSIZE

Definition at line 313 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_AWVALID

bit S_AXI_GP1_AWVALID

Definition at line 303 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_BID

bit<5 : 0> S_AXI_GP1_BID

Definition at line 299 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_BREADY

bit S_AXI_GP1_BREADY

Definition at line 304 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_BRESP

bit<1 : 0> S_AXI_GP1_BRESP

Definition at line 296 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_BVALID

bit S_AXI_GP1_BVALID

Definition at line 292 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_RDATA

bit<31 : 0> S_AXI_GP1_RDATA

Definition at line 298 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_RID

bit<5 : 0> S_AXI_GP1_RID

Definition at line 300 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_RLAST

bit S_AXI_GP1_RLAST

Definition at line 293 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_RREADY

bit S_AXI_GP1_RREADY

Definition at line 305 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_RRESP

bit<1 : 0> S_AXI_GP1_RRESP

Definition at line 297 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_RVALID

bit S_AXI_GP1_RVALID

Definition at line 294 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_WDATA

bit<31 : 0> S_AXI_GP1_WDATA

Definition at line 318 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_WID

bit<5 : 0> S_AXI_GP1_WID

Definition at line 328 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_WLAST

bit S_AXI_GP1_WLAST

Definition at line 306 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_WREADY

bit S_AXI_GP1_WREADY

Definition at line 295 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_WSTRB

bit<3 : 0> S_AXI_GP1_WSTRB

Definition at line 325 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_GP1_WVALID

bit S_AXI_GP1_WVALID

Definition at line 307 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP0_ACLK

bit S_AXI_HP0_ACLK

Definition at line 385 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARADDR

bit<31 : 0> S_AXI_HP0_ARADDR

Definition at line 402 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARBURST

bit<1 : 0> S_AXI_HP0_ARBURST

Definition at line 394 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARCACHE

bit<3 : 0> S_AXI_HP0_ARCACHE

Definition at line 404 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARID

bit<5 : 0> S_AXI_HP0_ARID

Definition at line 410 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARLEN

bit<3 : 0> S_AXI_HP0_ARLEN

Definition at line 405 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARLOCK

bit<1 : 0> S_AXI_HP0_ARLOCK

Definition at line 395 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARPROT

bit<2 : 0> S_AXI_HP0_ARPROT

Definition at line 400 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARQOS

bit<3 : 0> S_AXI_HP0_ARQOS

Definition at line 406 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARREADY

bit S_AXI_HP0_ARREADY

Definition at line 370 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARSIZE

bit<2 : 0> S_AXI_HP0_ARSIZE

Definition at line 396 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_ARVALID

bit S_AXI_HP0_ARVALID

Definition at line 386 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWADDR

bit<31 : 0> S_AXI_HP0_AWADDR

Definition at line 403 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWBURST

bit<1 : 0> S_AXI_HP0_AWBURST

Definition at line 397 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWCACHE

bit<3 : 0> S_AXI_HP0_AWCACHE

Definition at line 407 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWID

bit<5 : 0> S_AXI_HP0_AWID

Definition at line 411 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWLEN

bit<3 : 0> S_AXI_HP0_AWLEN

Definition at line 408 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWLOCK

bit<1 : 0> S_AXI_HP0_AWLOCK

Definition at line 398 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWPROT

bit<2 : 0> S_AXI_HP0_AWPROT

Definition at line 401 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWQOS

bit<3 : 0> S_AXI_HP0_AWQOS

Definition at line 409 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWREADY

bit S_AXI_HP0_AWREADY

Definition at line 371 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWSIZE

bit<2 : 0> S_AXI_HP0_AWSIZE

Definition at line 399 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_AWVALID

bit S_AXI_HP0_AWVALID

Definition at line 387 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_BID

bit<5 : 0> S_AXI_HP0_BID

Definition at line 378 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_BREADY

bit S_AXI_HP0_BREADY

Definition at line 388 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_BRESP

bit<1 : 0> S_AXI_HP0_BRESP

Definition at line 376 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_BVALID

bit S_AXI_HP0_BVALID

Definition at line 372 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RACOUNT

bit<2 : 0> S_AXI_HP0_RACOUNT

Definition at line 383 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RCOUNT

bit<7 : 0> S_AXI_HP0_RCOUNT

Definition at line 381 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RDATA

bit<63 : 0> S_AXI_HP0_RDATA

Definition at line 380 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RDISSUECAP1_EN

bit S_AXI_HP0_RDISSUECAP1_EN

Definition at line 389 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RID

bit<5 : 0> S_AXI_HP0_RID

Definition at line 379 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RLAST

bit S_AXI_HP0_RLAST

Definition at line 373 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RREADY

bit S_AXI_HP0_RREADY

Definition at line 390 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RRESP

bit<1 : 0> S_AXI_HP0_RRESP

Definition at line 377 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_RVALID

bit S_AXI_HP0_RVALID

Definition at line 374 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WACOUNT

bit<5 : 0> S_AXI_HP0_WACOUNT

Definition at line 384 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WCOUNT

bit<7 : 0> S_AXI_HP0_WCOUNT

Definition at line 382 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WDATA

bit<63 : 0> S_AXI_HP0_WDATA

Definition at line 413 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WID

bit<5 : 0> S_AXI_HP0_WID

Definition at line 412 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WLAST

bit S_AXI_HP0_WLAST

Definition at line 391 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WREADY

bit S_AXI_HP0_WREADY

Definition at line 375 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WRISSUECAP1_EN

bit S_AXI_HP0_WRISSUECAP1_EN

Definition at line 392 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WSTRB

bit<7 : 0> S_AXI_HP0_WSTRB

Definition at line 414 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP0_WVALID

bit S_AXI_HP0_WVALID

Definition at line 393 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

S_AXI_HP1_ACLK

bit S_AXI_HP1_ACLK

Definition at line 430 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARADDR

bit<31 : 0> S_AXI_HP1_ARADDR

Definition at line 447 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARBURST

bit<1 : 0> S_AXI_HP1_ARBURST

Definition at line 439 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARCACHE

bit<3 : 0> S_AXI_HP1_ARCACHE

Definition at line 449 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARID

bit<5 : 0> S_AXI_HP1_ARID

Definition at line 455 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARLEN

bit<3 : 0> S_AXI_HP1_ARLEN

Definition at line 450 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARLOCK

bit<1 : 0> S_AXI_HP1_ARLOCK

Definition at line 440 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARPROT

bit<2 : 0> S_AXI_HP1_ARPROT

Definition at line 445 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARQOS

bit<3 : 0> S_AXI_HP1_ARQOS

Definition at line 451 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARREADY

bit S_AXI_HP1_ARREADY

Definition at line 415 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARSIZE

bit<2 : 0> S_AXI_HP1_ARSIZE

Definition at line 441 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_ARVALID

bit S_AXI_HP1_ARVALID

Definition at line 431 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWADDR

bit<31 : 0> S_AXI_HP1_AWADDR

Definition at line 448 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWBURST

bit<1 : 0> S_AXI_HP1_AWBURST

Definition at line 442 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWCACHE

bit<3 : 0> S_AXI_HP1_AWCACHE

Definition at line 452 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWID

bit<5 : 0> S_AXI_HP1_AWID

Definition at line 456 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWLEN

bit<3 : 0> S_AXI_HP1_AWLEN

Definition at line 453 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWLOCK

bit<1 : 0> S_AXI_HP1_AWLOCK

Definition at line 443 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWPROT

bit<2 : 0> S_AXI_HP1_AWPROT

Definition at line 446 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWQOS

bit<3 : 0> S_AXI_HP1_AWQOS

Definition at line 454 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWREADY

bit S_AXI_HP1_AWREADY

Definition at line 416 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWSIZE

bit<2 : 0> S_AXI_HP1_AWSIZE

Definition at line 444 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_AWVALID

bit S_AXI_HP1_AWVALID

Definition at line 432 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_BID

bit<5 : 0> S_AXI_HP1_BID

Definition at line 423 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_BREADY

bit S_AXI_HP1_BREADY

Definition at line 433 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_BRESP

bit<1 : 0> S_AXI_HP1_BRESP

Definition at line 421 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_BVALID

bit S_AXI_HP1_BVALID

Definition at line 417 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RACOUNT

bit<2 : 0> S_AXI_HP1_RACOUNT

Definition at line 428 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RCOUNT

bit<7 : 0> S_AXI_HP1_RCOUNT

Definition at line 426 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RDATA

bit<63 : 0> S_AXI_HP1_RDATA

Definition at line 425 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RDISSUECAP1_EN

bit S_AXI_HP1_RDISSUECAP1_EN

Definition at line 434 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RID

bit<5 : 0> S_AXI_HP1_RID

Definition at line 424 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RLAST

bit S_AXI_HP1_RLAST

Definition at line 418 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RREADY

bit S_AXI_HP1_RREADY

Definition at line 435 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RRESP

bit<1 : 0> S_AXI_HP1_RRESP

Definition at line 422 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_RVALID

bit S_AXI_HP1_RVALID

Definition at line 419 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WACOUNT

bit<5 : 0> S_AXI_HP1_WACOUNT

Definition at line 429 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WCOUNT

bit<7 : 0> S_AXI_HP1_WCOUNT

Definition at line 427 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WDATA

bit<63 : 0> S_AXI_HP1_WDATA

Definition at line 458 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WID

bit<5 : 0> S_AXI_HP1_WID

Definition at line 457 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WLAST

bit S_AXI_HP1_WLAST

Definition at line 436 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WREADY

bit S_AXI_HP1_WREADY

Definition at line 420 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WRISSUECAP1_EN

bit S_AXI_HP1_WRISSUECAP1_EN

Definition at line 437 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WSTRB

bit<7 : 0> S_AXI_HP1_WSTRB

Definition at line 459 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP1_WVALID

bit S_AXI_HP1_WVALID

Definition at line 438 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ACLK

bit S_AXI_HP2_ACLK

Definition at line 475 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARADDR

bit<31 : 0> S_AXI_HP2_ARADDR

Definition at line 492 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARBURST

bit<1 : 0> S_AXI_HP2_ARBURST

Definition at line 484 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARCACHE

bit<3 : 0> S_AXI_HP2_ARCACHE

Definition at line 494 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARID

bit<5 : 0> S_AXI_HP2_ARID

Definition at line 500 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARLEN

bit<3 : 0> S_AXI_HP2_ARLEN

Definition at line 495 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARLOCK

bit<1 : 0> S_AXI_HP2_ARLOCK

Definition at line 485 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARPROT

bit<2 : 0> S_AXI_HP2_ARPROT

Definition at line 490 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARQOS

bit<3 : 0> S_AXI_HP2_ARQOS

Definition at line 496 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARREADY

bit S_AXI_HP2_ARREADY

Definition at line 460 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARSIZE

bit<2 : 0> S_AXI_HP2_ARSIZE

Definition at line 486 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_ARVALID

bit S_AXI_HP2_ARVALID

Definition at line 476 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWADDR

bit<31 : 0> S_AXI_HP2_AWADDR

Definition at line 493 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWBURST

bit<1 : 0> S_AXI_HP2_AWBURST

Definition at line 487 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWCACHE

bit<3 : 0> S_AXI_HP2_AWCACHE

Definition at line 497 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWID

bit<5 : 0> S_AXI_HP2_AWID

Definition at line 501 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWLEN

bit<3 : 0> S_AXI_HP2_AWLEN

Definition at line 498 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWLOCK

bit<1 : 0> S_AXI_HP2_AWLOCK

Definition at line 488 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWPROT

bit<2 : 0> S_AXI_HP2_AWPROT

Definition at line 491 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWQOS

bit<3 : 0> S_AXI_HP2_AWQOS

Definition at line 499 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWREADY

bit S_AXI_HP2_AWREADY

Definition at line 461 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWSIZE

bit<2 : 0> S_AXI_HP2_AWSIZE

Definition at line 489 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_AWVALID

bit S_AXI_HP2_AWVALID

Definition at line 477 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_BID

bit<5 : 0> S_AXI_HP2_BID

Definition at line 468 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_BREADY

bit S_AXI_HP2_BREADY

Definition at line 478 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_BRESP

bit<1 : 0> S_AXI_HP2_BRESP

Definition at line 466 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_BVALID

bit S_AXI_HP2_BVALID

Definition at line 462 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RACOUNT

bit<2 : 0> S_AXI_HP2_RACOUNT

Definition at line 473 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RCOUNT

bit<7 : 0> S_AXI_HP2_RCOUNT

Definition at line 471 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RDATA

bit<63 : 0> S_AXI_HP2_RDATA

Definition at line 470 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RDISSUECAP1_EN

bit S_AXI_HP2_RDISSUECAP1_EN

Definition at line 479 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RID

bit<5 : 0> S_AXI_HP2_RID

Definition at line 469 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RLAST

bit S_AXI_HP2_RLAST

Definition at line 463 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RREADY

bit S_AXI_HP2_RREADY

Definition at line 480 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RRESP

bit<1 : 0> S_AXI_HP2_RRESP

Definition at line 467 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_RVALID

bit S_AXI_HP2_RVALID

Definition at line 464 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WACOUNT

bit<5 : 0> S_AXI_HP2_WACOUNT

Definition at line 474 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WCOUNT

bit<7 : 0> S_AXI_HP2_WCOUNT

Definition at line 472 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WDATA

bit<63 : 0> S_AXI_HP2_WDATA

Definition at line 503 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WID

bit<5 : 0> S_AXI_HP2_WID

Definition at line 502 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WLAST

bit S_AXI_HP2_WLAST

Definition at line 481 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WREADY

bit S_AXI_HP2_WREADY

Definition at line 465 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WRISSUECAP1_EN

bit S_AXI_HP2_WRISSUECAP1_EN

Definition at line 482 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WSTRB

bit<7 : 0> S_AXI_HP2_WSTRB

Definition at line 504 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP2_WVALID

bit S_AXI_HP2_WVALID

Definition at line 483 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ACLK

bit S_AXI_HP3_ACLK

Definition at line 520 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARADDR

bit<31 : 0> S_AXI_HP3_ARADDR

Definition at line 537 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARBURST

bit<1 : 0> S_AXI_HP3_ARBURST

Definition at line 529 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARCACHE

bit<3 : 0> S_AXI_HP3_ARCACHE

Definition at line 539 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARID

bit<5 : 0> S_AXI_HP3_ARID

Definition at line 545 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARLEN

bit<3 : 0> S_AXI_HP3_ARLEN

Definition at line 540 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARLOCK

bit<1 : 0> S_AXI_HP3_ARLOCK

Definition at line 530 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARPROT

bit<2 : 0> S_AXI_HP3_ARPROT

Definition at line 535 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARQOS

bit<3 : 0> S_AXI_HP3_ARQOS

Definition at line 541 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARREADY

bit S_AXI_HP3_ARREADY

Definition at line 505 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARSIZE

bit<2 : 0> S_AXI_HP3_ARSIZE

Definition at line 531 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_ARVALID

bit S_AXI_HP3_ARVALID

Definition at line 521 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWADDR

bit<31 : 0> S_AXI_HP3_AWADDR

Definition at line 538 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWBURST

bit<1 : 0> S_AXI_HP3_AWBURST

Definition at line 532 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWCACHE

bit<3 : 0> S_AXI_HP3_AWCACHE

Definition at line 542 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWID

bit<5 : 0> S_AXI_HP3_AWID

Definition at line 546 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWLEN

bit<3 : 0> S_AXI_HP3_AWLEN

Definition at line 543 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWLOCK

bit<1 : 0> S_AXI_HP3_AWLOCK

Definition at line 533 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWPROT

bit<2 : 0> S_AXI_HP3_AWPROT

Definition at line 536 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWQOS

bit<3 : 0> S_AXI_HP3_AWQOS

Definition at line 544 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWREADY

bit S_AXI_HP3_AWREADY

Definition at line 506 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWSIZE

bit<2 : 0> S_AXI_HP3_AWSIZE

Definition at line 534 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_AWVALID

bit S_AXI_HP3_AWVALID

Definition at line 522 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_BID

bit<5 : 0> S_AXI_HP3_BID

Definition at line 513 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_BREADY

bit S_AXI_HP3_BREADY

Definition at line 523 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_BRESP

bit<1 : 0> S_AXI_HP3_BRESP

Definition at line 511 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_BVALID

bit S_AXI_HP3_BVALID

Definition at line 507 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RACOUNT

bit<2 : 0> S_AXI_HP3_RACOUNT

Definition at line 518 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RCOUNT

bit<7 : 0> S_AXI_HP3_RCOUNT

Definition at line 516 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RDATA

bit<63 : 0> S_AXI_HP3_RDATA

Definition at line 515 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RDISSUECAP1_EN

bit S_AXI_HP3_RDISSUECAP1_EN

Definition at line 524 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RID

bit<5 : 0> S_AXI_HP3_RID

Definition at line 514 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RLAST

bit S_AXI_HP3_RLAST

Definition at line 508 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RREADY

bit S_AXI_HP3_RREADY

Definition at line 525 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RRESP

bit<1 : 0> S_AXI_HP3_RRESP

Definition at line 512 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_RVALID

bit S_AXI_HP3_RVALID

Definition at line 509 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WACOUNT

bit<5 : 0> S_AXI_HP3_WACOUNT

Definition at line 519 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WCOUNT

bit<7 : 0> S_AXI_HP3_WCOUNT

Definition at line 517 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WDATA

bit<63 : 0> S_AXI_HP3_WDATA

Definition at line 548 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WID

bit<5 : 0> S_AXI_HP3_WID

Definition at line 547 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WLAST

bit S_AXI_HP3_WLAST

Definition at line 526 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WREADY

bit S_AXI_HP3_WREADY

Definition at line 510 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WRISSUECAP1_EN

bit S_AXI_HP3_WRISSUECAP1_EN

Definition at line 527 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WSTRB

bit<7 : 0> S_AXI_HP3_WSTRB

Definition at line 549 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

S_AXI_HP3_WVALID

bit S_AXI_HP3_WVALID

Definition at line 528 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_BUSPOW

bit SDIO0_BUSPOW

Definition at line 89 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_BUSVOLT

bit<2 : 0> SDIO0_BUSVOLT

Definition at line 90 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_CDN

bit SDIO0_CDN

Definition at line 87 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_CLK

bit SDIO0_CLK

Definition at line 78 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_CLK_FB

bit SDIO0_CLK_FB

Definition at line 79 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_CMD_I

bit SDIO0_CMD_I

Definition at line 81 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_CMD_O

bit SDIO0_CMD_O

Definition at line 80 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_CMD_T

bit SDIO0_CMD_T

Definition at line 82 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_DATA_I

bit<3 : 0> SDIO0_DATA_I

Definition at line 83 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_DATA_O

bit<3 : 0> SDIO0_DATA_O

Definition at line 84 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_DATA_T

bit<3 : 0> SDIO0_DATA_T

Definition at line 85 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_LED

bit SDIO0_LED

Definition at line 86 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO0_WP

bit SDIO0_WP

Definition at line 88 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_BUSPOW

bit SDIO1_BUSPOW

Definition at line 102 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_BUSVOLT

bit<2 : 0> SDIO1_BUSVOLT

Definition at line 103 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_CDN

bit SDIO1_CDN

Definition at line 100 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_CLK

bit SDIO1_CLK

Definition at line 91 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_CLK_FB

bit SDIO1_CLK_FB

Definition at line 92 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_CMD_I

bit SDIO1_CMD_I

Definition at line 94 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_CMD_O

bit SDIO1_CMD_O

Definition at line 93 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_CMD_T

bit SDIO1_CMD_T

Definition at line 95 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_DATA_I

bit<3 : 0> SDIO1_DATA_I

Definition at line 96 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_DATA_O

bit<3 : 0> SDIO1_DATA_O

Definition at line 97 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_DATA_T

bit<3 : 0> SDIO1_DATA_T

Definition at line 98 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_LED

bit SDIO1_LED

Definition at line 99 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SDIO1_WP

bit SDIO1_WP

Definition at line 101 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_MISO_I

bit SPI0_MISO_I

Definition at line 110 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_MISO_O

bit SPI0_MISO_O

Definition at line 111 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_MISO_T

bit SPI0_MISO_T

Definition at line 112 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_MOSI_I

bit SPI0_MOSI_I

Definition at line 107 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_MOSI_O

bit SPI0_MOSI_O

Definition at line 108 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_MOSI_T

bit SPI0_MOSI_T

Definition at line 109 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SCLK_I

bit SPI0_SCLK_I

Definition at line 104 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SCLK_O

bit SPI0_SCLK_O

Definition at line 105 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SCLK_T

bit SPI0_SCLK_T

Definition at line 106 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SS1_O

bit SPI0_SS1_O

Definition at line 115 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SS2_O

bit SPI0_SS2_O

Definition at line 116 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SS_I

bit SPI0_SS_I

Definition at line 113 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SS_O

bit SPI0_SS_O

Definition at line 114 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI0_SS_T

bit SPI0_SS_T

Definition at line 117 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_MISO_I

bit SPI1_MISO_I

Definition at line 124 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_MISO_O

bit SPI1_MISO_O

Definition at line 125 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_MISO_T

bit SPI1_MISO_T

Definition at line 126 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_MOSI_I

bit SPI1_MOSI_I

Definition at line 121 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_MOSI_O

bit SPI1_MOSI_O

Definition at line 122 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_MOSI_T

bit SPI1_MOSI_T

Definition at line 123 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SCLK_I

bit SPI1_SCLK_I

Definition at line 118 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SCLK_O

bit SPI1_SCLK_O

Definition at line 119 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SCLK_T

bit SPI1_SCLK_T

Definition at line 120 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SS1_O

bit SPI1_SS1_O

Definition at line 129 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SS2_O

bit SPI1_SS2_O

Definition at line 130 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SS_I

bit SPI1_SS_I

Definition at line 127 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SS_O

bit SPI1_SS_O

Definition at line 128 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SPI1_SS_T

bit SPI1_SS_T

Definition at line 131 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

SRAM_INTIN

bit SRAM_INTIN

Definition at line 172 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TRACE_CLK

bit TRACE_CLK

Definition at line 162 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TRACE_CLK_OUT

bit TRACE_CLK_OUT

Definition at line 163 of file design_1_processing_system7_0_0.sv.

TRACE_CTL

bit TRACE_CTL

Definition at line 164 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TRACE_DATA

bit<1 : 0> TRACE_DATA

Definition at line 165 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC0_CLK0_IN

bit TTC0_CLK0_IN

Definition at line 151 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC0_CLK1_IN

bit TTC0_CLK1_IN

Definition at line 152 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC0_CLK2_IN

bit TTC0_CLK2_IN

Definition at line 153 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC0_WAVE0_OUT

bit TTC0_WAVE0_OUT

Definition at line 148 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

TTC0_WAVE1_OUT

bit TTC0_WAVE1_OUT

Definition at line 149 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

TTC0_WAVE2_OUT

bit TTC0_WAVE2_OUT

Definition at line 150 of file design_1_processing_system7_0_0.sv.

Referenced by design_1_processing_system7_0_0(), and processing_system7_vip_v1_0_10().

TTC1_CLK0_IN

bit TTC1_CLK0_IN

Definition at line 157 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC1_CLK1_IN

bit TTC1_CLK1_IN

Definition at line 158 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC1_CLK2_IN

bit TTC1_CLK2_IN

Definition at line 159 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC1_WAVE0_OUT

bit TTC1_WAVE0_OUT

Definition at line 154 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC1_WAVE1_OUT

bit TTC1_WAVE1_OUT

Definition at line 155 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

TTC1_WAVE2_OUT

bit TTC1_WAVE2_OUT

Definition at line 156 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_CTSN

bit UART0_CTSN

Definition at line 135 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_DCDN

bit UART0_DCDN

Definition at line 136 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_DSRN

bit UART0_DSRN

Definition at line 137 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_DTRN

bit UART0_DTRN

Definition at line 132 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_RIN

bit UART0_RIN

Definition at line 138 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_RTSN

bit UART0_RTSN

Definition at line 133 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_RX

bit UART0_RX

Definition at line 139 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART0_TX

bit UART0_TX

Definition at line 134 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_CTSN

bit UART1_CTSN

Definition at line 143 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_DCDN

bit UART1_DCDN

Definition at line 144 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_DSRN

bit UART1_DSRN

Definition at line 145 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_DTRN

bit UART1_DTRN

Definition at line 140 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_RIN

bit UART1_RIN

Definition at line 146 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_RTSN

bit UART1_RTSN

Definition at line 141 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_RX

bit UART1_RX

Definition at line 147 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

UART1_TX

bit UART1_TX

Definition at line 142 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

USB0_PORT_INDCTL

bit<1 : 0> USB0_PORT_INDCTL

Definition at line 166 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

USB0_VBUS_PWRFAULT

bit USB0_VBUS_PWRFAULT

Definition at line 168 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

USB0_VBUS_PWRSELECT

bit USB0_VBUS_PWRSELECT

Definition at line 167 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

USB1_PORT_INDCTL

bit<1 : 0> USB1_PORT_INDCTL

Definition at line 169 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

USB1_VBUS_PWRFAULT

bit USB1_VBUS_PWRFAULT

Definition at line 171 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

USB1_VBUS_PWRSELECT

bit USB1_VBUS_PWRSELECT

Definition at line 170 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

WDT_CLK_IN

bit WDT_CLK_IN

Definition at line 160 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().

WDT_RST_OUT

bit WDT_RST_OUT

Definition at line 161 of file design_1_processing_system7_0_0.sv.

Referenced by processing_system7_vip_v1_0_10().