SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_processing_system7_0_0_sc.h
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1 #ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
2 #define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
3 
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51 
52 
53 #ifndef XTLM
54 #include "xtlm.h"
55 #endif
56 #ifndef SYSTEMC_INCLUDED
57 #include <systemc>
58 #endif
59 
60 #if defined(_MSC_VER)
61 #define DllExport __declspec(dllexport)
62 #elif defined(__GNUC__)
63 #define DllExport __attribute__ ((visibility("default")))
64 #else
65 #define DllExport
66 #endif
67 
69 
70 class DllExport design_1_processing_system7_0_0_sc : public sc_core::sc_module
71 {
72 public:
73 
74  design_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
76 
77  // module socket-to-socket AXI TLM interfaces
78 
79  xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
80  xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
81  xtlm::xtlm_aximm_target_socket* S_AXI_HP0_rd_socket;
82  xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
83 
84  // module socket-to-socket TLM interfaces
85 
86 
87 protected:
88 
90 
91 private:
92 
95 
96 };
97 
98 #endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
design_1_processing_system7_0_0_sc
Definition: design_1_processing_system7_0_0_sc.h:70
design_1_processing_system7_0_0_sc::mp_impl
processing_system7_v5_5_tlm * mp_impl
Definition: design_1_processing_system7_0_0_sc.h:89
DllExport
#define DllExport
Definition: design_1_processing_system7_0_0_sc.h:65
design_1_processing_system7_0_0_sc::M_AXI_GP0_rd_socket
xtlm::xtlm_aximm_initiator_socket * M_AXI_GP0_rd_socket
Definition: design_1_processing_system7_0_0_sc.h:79
design_1_processing_system7_0_0_sc::M_AXI_GP0_wr_socket
xtlm::xtlm_aximm_initiator_socket * M_AXI_GP0_wr_socket
Definition: design_1_processing_system7_0_0_sc.h:80
design_1_processing_system7_0_0_sc::S_AXI_HP0_wr_socket
xtlm::xtlm_aximm_target_socket * S_AXI_HP0_wr_socket
Definition: design_1_processing_system7_0_0_sc.h:82
processing_system7_v5_5_tlm
Definition: processing_system7_v5_5_tlm.h:133
design_1_processing_system7_0_0_sc::S_AXI_HP0_rd_socket
xtlm::xtlm_aximm_target_socket * S_AXI_HP0_rd_socket
Definition: design_1_processing_system7_0_0_sc.h:81