SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_processing_system7_0_0.cpp
Go to the documentation of this file.
1 // (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
2 //
3 // This file contains confidential and proprietary information
4 // of Xilinx, Inc. and is protected under U.S. and
5 // international copyright and other intellectual property
6 // laws.
7 //
8 // DISCLAIMER
9 // This disclaimer is not a license and does not grant any
10 // rights to the materials distributed herewith. Except as
11 // otherwise provided in a valid license issued to you by
12 // Xilinx, and to the maximum extent permitted by applicable
13 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
14 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
15 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
16 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
17 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
18 // (2) Xilinx shall not be liable (whether in contract or tort,
19 // including negligence, or under any other theory of
20 // liability) for any loss or damage of any kind or nature
21 // related to, arising under or in connection with these
22 // materials, including for any direct, or any indirect,
23 // special, incidental, or consequential loss or damage
24 // (including loss of data, profits, goodwill, or any type of
25 // loss or damage suffered as a result of any action brought
26 // by a third party) even if such damage or loss was
27 // reasonably foreseeable or Xilinx had been advised of the
28 // possibility of the same.
29 //
30 // CRITICAL APPLICATIONS
31 // Xilinx products are not designed or intended to be fail-
32 // safe, or for use in any application requiring fail-safe
33 // performance, such as life-support or safety devices or
34 // systems, Class III medical devices, nuclear facilities,
35 // applications related to the deployment of airbags, or any
36 // other applications that could lead to death, personal
37 // injury, or severe property or environmental damage
38 // (individually and collectively, "Critical
39 // Applications"). Customer assumes the sole risk and
40 // liability of any use of Xilinx products in Critical
41 // Applications, subject only to applicable laws and
42 // regulations governing limitations on product liability.
43 //
44 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
45 // PART OF THIS FILE AT ALL TIMES.
46 //
47 // DO NOT MODIFY THIS FILE.
48 
49 
50 #include "design_1_processing_system7_0_0_sc.h"
51 
52 #include "design_1_processing_system7_0_0.h"
53 
54 #include "processing_system7_v5_5_tlm.h"
55 
56 #include <map>
57 #include <string>
58 
59 
60 
61 
62 
63 #ifdef XILINX_SIMULATOR
64 design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), ENET0_GMII_TX_EN("ENET0_GMII_TX_EN"), ENET0_GMII_TX_ER("ENET0_GMII_TX_ER"), ENET0_MDIO_MDC("ENET0_MDIO_MDC"), ENET0_MDIO_O("ENET0_MDIO_O"), ENET0_MDIO_T("ENET0_MDIO_T"), ENET0_GMII_TXD("ENET0_GMII_TXD"), ENET0_GMII_COL("ENET0_GMII_COL"), ENET0_GMII_CRS("ENET0_GMII_CRS"), ENET0_GMII_RX_CLK("ENET0_GMII_RX_CLK"), ENET0_GMII_RX_DV("ENET0_GMII_RX_DV"), ENET0_GMII_RX_ER("ENET0_GMII_RX_ER"), ENET0_GMII_TX_CLK("ENET0_GMII_TX_CLK"), ENET0_MDIO_I("ENET0_MDIO_I"), ENET0_EXT_INTIN("ENET0_EXT_INTIN"), ENET0_GMII_RXD("ENET0_GMII_RXD"), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), TTC0_WAVE0_OUT("TTC0_WAVE0_OUT"), TTC0_WAVE1_OUT("TTC0_WAVE1_OUT"), TTC0_WAVE2_OUT("TTC0_WAVE2_OUT"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), S_AXI_HP0_ARREADY("S_AXI_HP0_ARREADY"), S_AXI_HP0_AWREADY("S_AXI_HP0_AWREADY"), S_AXI_HP0_BVALID("S_AXI_HP0_BVALID"), S_AXI_HP0_RLAST("S_AXI_HP0_RLAST"), S_AXI_HP0_RVALID("S_AXI_HP0_RVALID"), S_AXI_HP0_WREADY("S_AXI_HP0_WREADY"), S_AXI_HP0_BRESP("S_AXI_HP0_BRESP"), S_AXI_HP0_RRESP("S_AXI_HP0_RRESP"), S_AXI_HP0_BID("S_AXI_HP0_BID"), S_AXI_HP0_RID("S_AXI_HP0_RID"), S_AXI_HP0_RDATA("S_AXI_HP0_RDATA"), S_AXI_HP0_RCOUNT("S_AXI_HP0_RCOUNT"), S_AXI_HP0_WCOUNT("S_AXI_HP0_WCOUNT"), S_AXI_HP0_RACOUNT("S_AXI_HP0_RACOUNT"), S_AXI_HP0_WACOUNT("S_AXI_HP0_WACOUNT"), S_AXI_HP0_ACLK("S_AXI_HP0_ACLK"), S_AXI_HP0_ARVALID("S_AXI_HP0_ARVALID"), S_AXI_HP0_AWVALID("S_AXI_HP0_AWVALID"), S_AXI_HP0_BREADY("S_AXI_HP0_BREADY"), S_AXI_HP0_RDISSUECAP1_EN("S_AXI_HP0_RDISSUECAP1_EN"), S_AXI_HP0_RREADY("S_AXI_HP0_RREADY"), S_AXI_HP0_WLAST("S_AXI_HP0_WLAST"), S_AXI_HP0_WRISSUECAP1_EN("S_AXI_HP0_WRISSUECAP1_EN"), S_AXI_HP0_WVALID("S_AXI_HP0_WVALID"), S_AXI_HP0_ARBURST("S_AXI_HP0_ARBURST"), S_AXI_HP0_ARLOCK("S_AXI_HP0_ARLOCK"), S_AXI_HP0_ARSIZE("S_AXI_HP0_ARSIZE"), S_AXI_HP0_AWBURST("S_AXI_HP0_AWBURST"), S_AXI_HP0_AWLOCK("S_AXI_HP0_AWLOCK"), S_AXI_HP0_AWSIZE("S_AXI_HP0_AWSIZE"), S_AXI_HP0_ARPROT("S_AXI_HP0_ARPROT"), S_AXI_HP0_AWPROT("S_AXI_HP0_AWPROT"), S_AXI_HP0_ARADDR("S_AXI_HP0_ARADDR"), S_AXI_HP0_AWADDR("S_AXI_HP0_AWADDR"), S_AXI_HP0_ARCACHE("S_AXI_HP0_ARCACHE"), S_AXI_HP0_ARLEN("S_AXI_HP0_ARLEN"), S_AXI_HP0_ARQOS("S_AXI_HP0_ARQOS"), S_AXI_HP0_AWCACHE("S_AXI_HP0_AWCACHE"), S_AXI_HP0_AWLEN("S_AXI_HP0_AWLEN"), S_AXI_HP0_AWQOS("S_AXI_HP0_AWQOS"), S_AXI_HP0_ARID("S_AXI_HP0_ARID"), S_AXI_HP0_AWID("S_AXI_HP0_AWID"), S_AXI_HP0_WID("S_AXI_HP0_WID"), S_AXI_HP0_WDATA("S_AXI_HP0_WDATA"), S_AXI_HP0_WSTRB("S_AXI_HP0_WSTRB"), IRQ_F2P("IRQ_F2P"), FCLK_CLK0("FCLK_CLK0"), FCLK_CLK1("FCLK_CLK1"), FCLK_CLK2("FCLK_CLK2"), FCLK_CLK3("FCLK_CLK3"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
65 {
66 
67  // initialize pins
68  mp_impl->ENET0_GMII_TX_EN(ENET0_GMII_TX_EN);
69  mp_impl->ENET0_GMII_TX_ER(ENET0_GMII_TX_ER);
70  mp_impl->ENET0_MDIO_MDC(ENET0_MDIO_MDC);
71  mp_impl->ENET0_MDIO_O(ENET0_MDIO_O);
72  mp_impl->ENET0_MDIO_T(ENET0_MDIO_T);
73  mp_impl->ENET0_GMII_TXD(ENET0_GMII_TXD);
74  mp_impl->ENET0_GMII_COL(ENET0_GMII_COL);
75  mp_impl->ENET0_GMII_CRS(ENET0_GMII_CRS);
76  mp_impl->ENET0_GMII_RX_CLK(ENET0_GMII_RX_CLK);
77  mp_impl->ENET0_GMII_RX_DV(ENET0_GMII_RX_DV);
78  mp_impl->ENET0_GMII_RX_ER(ENET0_GMII_RX_ER);
79  mp_impl->ENET0_GMII_TX_CLK(ENET0_GMII_TX_CLK);
80  mp_impl->ENET0_MDIO_I(ENET0_MDIO_I);
81  mp_impl->ENET0_EXT_INTIN(ENET0_EXT_INTIN);
82  mp_impl->ENET0_GMII_RXD(ENET0_GMII_RXD);
83  mp_impl->GPIO_I(GPIO_I);
84  mp_impl->GPIO_O(GPIO_O);
85  mp_impl->GPIO_T(GPIO_T);
86  mp_impl->TTC0_WAVE0_OUT(TTC0_WAVE0_OUT);
87  mp_impl->TTC0_WAVE1_OUT(TTC0_WAVE1_OUT);
88  mp_impl->TTC0_WAVE2_OUT(TTC0_WAVE2_OUT);
89  mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
90  mp_impl->S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT);
91  mp_impl->S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT);
92  mp_impl->S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT);
93  mp_impl->S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT);
94  mp_impl->S_AXI_HP0_ACLK(S_AXI_HP0_ACLK);
95  mp_impl->S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN);
96  mp_impl->S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN);
97  mp_impl->IRQ_F2P(IRQ_F2P);
98  mp_impl->FCLK_CLK0(FCLK_CLK0);
99  mp_impl->FCLK_CLK1(FCLK_CLK1);
100  mp_impl->FCLK_CLK2(FCLK_CLK2);
101  mp_impl->FCLK_CLK3(FCLK_CLK3);
102  mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
103  mp_impl->MIO(MIO);
104  mp_impl->DDR_CAS_n(DDR_CAS_n);
105  mp_impl->DDR_CKE(DDR_CKE);
106  mp_impl->DDR_Clk_n(DDR_Clk_n);
107  mp_impl->DDR_Clk(DDR_Clk);
108  mp_impl->DDR_CS_n(DDR_CS_n);
109  mp_impl->DDR_DRSTB(DDR_DRSTB);
110  mp_impl->DDR_ODT(DDR_ODT);
111  mp_impl->DDR_RAS_n(DDR_RAS_n);
112  mp_impl->DDR_WEB(DDR_WEB);
113  mp_impl->DDR_BankAddr(DDR_BankAddr);
114  mp_impl->DDR_Addr(DDR_Addr);
115  mp_impl->DDR_VRN(DDR_VRN);
116  mp_impl->DDR_VRP(DDR_VRP);
117  mp_impl->DDR_DM(DDR_DM);
118  mp_impl->DDR_DQ(DDR_DQ);
119  mp_impl->DDR_DQS_n(DDR_DQS_n);
120  mp_impl->DDR_DQS(DDR_DQS);
121  mp_impl->PS_SRSTB(PS_SRSTB);
122  mp_impl->PS_CLK(PS_CLK);
123  mp_impl->PS_PORB(PS_PORB);
124 
125  // initialize transactors
126  mp_M_AXI_GP0_transactor = NULL;
127  mp_M_AXI_GP0_ARLOCK_converter = NULL;
128  mp_M_AXI_GP0_AWLOCK_converter = NULL;
129  mp_M_AXI_GP0_ARLEN_converter = NULL;
130  mp_M_AXI_GP0_AWLEN_converter = NULL;
131  mp_S_AXI_HP0_transactor = NULL;
132  mp_S_AXI_HP0_ARLOCK_converter = NULL;
133  mp_S_AXI_HP0_AWLOCK_converter = NULL;
134  mp_S_AXI_HP0_ARLEN_converter = NULL;
135  mp_S_AXI_HP0_AWLEN_converter = NULL;
136 
137  // initialize socket stubs
138 
139 }
140 
141 void design_1_processing_system7_0_0::before_end_of_elaboration()
142 {
143  // configure 'M_AXI_GP0' transactor
144 
145  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
146  {
147  // Instantiate Socket Stubs
148 
149  // 'M_AXI_GP0' transactor parameters
150  xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
151  M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
152  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
153  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
154  M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
155  M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
156  M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
157  M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
158  M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
159  M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
160  M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
161  M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
162  M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
163  M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
164  M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
165  M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
166  M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
167  M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
168  M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
169  M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
170  M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
171  M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
172  M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
173  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
174  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
175  M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
176  M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
177  M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
178  M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
179  M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.000");
180  M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
181  M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
182  M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
183 
184  mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
185 
186  // M_AXI_GP0' transactor ports
187 
188  mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
189  mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
190  mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
191  mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
192  mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
193  mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
194  mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
195  mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
196  mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
197  mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
198  mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
199  mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
200  mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
201  mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
202  mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
203  mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
204  mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
205  mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
206  mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
207  mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
208  mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
209  mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
210  mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
211  mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
212  mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
213  mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
214  mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
215  mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
216  mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
217  mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
218  mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
219  mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
220  mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
221  mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
222  mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
223  mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
224  mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
225  mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
226  mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
227  mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
228  mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
229  mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
230  mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
231  mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
232  mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
233  mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
234  mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
235  mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
236  mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
237  mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
238  m_M_AXI_GP0_transactor_rst_signal.write(1);
239  mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
240 
241  // M_AXI_GP0' transactor sockets
242 
243  mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
244  mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
245  }
246  else
247  {
248  }
249 
250  // configure 'S_AXI_HP0' transactor
251 
252  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
253  {
254  // Instantiate Socket Stubs
255 
256  // 'S_AXI_HP0' transactor parameters
257  xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
258  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
259  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
260  S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "64");
261  S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
262  S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
263  S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
264  S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
265  S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
266  S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
267  S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
268  S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
269  S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
270  S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
271  S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
272  S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
273  S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
274  S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
275  S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
276  S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
277  S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
278  S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
279  S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
280  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
281  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
282  S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
283  S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
284  S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
285  S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
286  S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.000");
287  S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
288  S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
289  S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
290 
291  mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
292 
293  // S_AXI_HP0' transactor ports
294 
295  mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
296  mp_S_AXI_HP0_transactor->AWREADY(S_AXI_HP0_AWREADY);
297  mp_S_AXI_HP0_transactor->BVALID(S_AXI_HP0_BVALID);
298  mp_S_AXI_HP0_transactor->RLAST(S_AXI_HP0_RLAST);
299  mp_S_AXI_HP0_transactor->RVALID(S_AXI_HP0_RVALID);
300  mp_S_AXI_HP0_transactor->WREADY(S_AXI_HP0_WREADY);
301  mp_S_AXI_HP0_transactor->BRESP(S_AXI_HP0_BRESP);
302  mp_S_AXI_HP0_transactor->RRESP(S_AXI_HP0_RRESP);
303  mp_S_AXI_HP0_transactor->BID(S_AXI_HP0_BID);
304  mp_S_AXI_HP0_transactor->RID(S_AXI_HP0_RID);
305  mp_S_AXI_HP0_transactor->RDATA(S_AXI_HP0_RDATA);
306  mp_S_AXI_HP0_transactor->ARVALID(S_AXI_HP0_ARVALID);
307  mp_S_AXI_HP0_transactor->AWVALID(S_AXI_HP0_AWVALID);
308  mp_S_AXI_HP0_transactor->BREADY(S_AXI_HP0_BREADY);
309  mp_S_AXI_HP0_transactor->RREADY(S_AXI_HP0_RREADY);
310  mp_S_AXI_HP0_transactor->WLAST(S_AXI_HP0_WLAST);
311  mp_S_AXI_HP0_transactor->WVALID(S_AXI_HP0_WVALID);
312  mp_S_AXI_HP0_transactor->ARBURST(S_AXI_HP0_ARBURST);
313  mp_S_AXI_HP0_ARLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_ARLOCK_converter");
314  mp_S_AXI_HP0_ARLOCK_converter->vector_in(S_AXI_HP0_ARLOCK);
315  mp_S_AXI_HP0_ARLOCK_converter->scalar_out(m_S_AXI_HP0_ARLOCK_converter_signal);
316  mp_S_AXI_HP0_transactor->ARLOCK(m_S_AXI_HP0_ARLOCK_converter_signal);
317  mp_S_AXI_HP0_transactor->ARSIZE(S_AXI_HP0_ARSIZE);
318  mp_S_AXI_HP0_transactor->AWBURST(S_AXI_HP0_AWBURST);
319  mp_S_AXI_HP0_AWLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_AWLOCK_converter");
320  mp_S_AXI_HP0_AWLOCK_converter->vector_in(S_AXI_HP0_AWLOCK);
321  mp_S_AXI_HP0_AWLOCK_converter->scalar_out(m_S_AXI_HP0_AWLOCK_converter_signal);
322  mp_S_AXI_HP0_transactor->AWLOCK(m_S_AXI_HP0_AWLOCK_converter_signal);
323  mp_S_AXI_HP0_transactor->AWSIZE(S_AXI_HP0_AWSIZE);
324  mp_S_AXI_HP0_transactor->ARPROT(S_AXI_HP0_ARPROT);
325  mp_S_AXI_HP0_transactor->AWPROT(S_AXI_HP0_AWPROT);
326  mp_S_AXI_HP0_transactor->ARADDR(S_AXI_HP0_ARADDR);
327  mp_S_AXI_HP0_transactor->AWADDR(S_AXI_HP0_AWADDR);
328  mp_S_AXI_HP0_transactor->ARCACHE(S_AXI_HP0_ARCACHE);
329  mp_S_AXI_HP0_ARLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_ARLEN_converter");
330  mp_S_AXI_HP0_ARLEN_converter->vector_in(S_AXI_HP0_ARLEN);
331  mp_S_AXI_HP0_ARLEN_converter->vector_out(m_S_AXI_HP0_ARLEN_converter_signal);
332  mp_S_AXI_HP0_transactor->ARLEN(m_S_AXI_HP0_ARLEN_converter_signal);
333  mp_S_AXI_HP0_transactor->ARQOS(S_AXI_HP0_ARQOS);
334  mp_S_AXI_HP0_transactor->AWCACHE(S_AXI_HP0_AWCACHE);
335  mp_S_AXI_HP0_AWLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_AWLEN_converter");
336  mp_S_AXI_HP0_AWLEN_converter->vector_in(S_AXI_HP0_AWLEN);
337  mp_S_AXI_HP0_AWLEN_converter->vector_out(m_S_AXI_HP0_AWLEN_converter_signal);
338  mp_S_AXI_HP0_transactor->AWLEN(m_S_AXI_HP0_AWLEN_converter_signal);
339  mp_S_AXI_HP0_transactor->AWQOS(S_AXI_HP0_AWQOS);
340  mp_S_AXI_HP0_transactor->ARID(S_AXI_HP0_ARID);
341  mp_S_AXI_HP0_transactor->AWID(S_AXI_HP0_AWID);
342  mp_S_AXI_HP0_transactor->WDATA(S_AXI_HP0_WDATA);
343  mp_S_AXI_HP0_transactor->WSTRB(S_AXI_HP0_WSTRB);
344  mp_S_AXI_HP0_transactor->CLK(S_AXI_HP0_ACLK);
345  m_S_AXI_HP0_transactor_rst_signal.write(1);
346  mp_S_AXI_HP0_transactor->RST(m_S_AXI_HP0_transactor_rst_signal);
347 
348  // S_AXI_HP0' transactor sockets
349 
350  mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
351  mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
352  }
353  else
354  {
355  }
356 
357 }
358 
359 #endif // XILINX_SIMULATOR
360 
361 
362 
363 
364 #ifdef XM_SYSTEMC
365 design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), ENET0_GMII_TX_EN("ENET0_GMII_TX_EN"), ENET0_GMII_TX_ER("ENET0_GMII_TX_ER"), ENET0_MDIO_MDC("ENET0_MDIO_MDC"), ENET0_MDIO_O("ENET0_MDIO_O"), ENET0_MDIO_T("ENET0_MDIO_T"), ENET0_GMII_TXD("ENET0_GMII_TXD"), ENET0_GMII_COL("ENET0_GMII_COL"), ENET0_GMII_CRS("ENET0_GMII_CRS"), ENET0_GMII_RX_CLK("ENET0_GMII_RX_CLK"), ENET0_GMII_RX_DV("ENET0_GMII_RX_DV"), ENET0_GMII_RX_ER("ENET0_GMII_RX_ER"), ENET0_GMII_TX_CLK("ENET0_GMII_TX_CLK"), ENET0_MDIO_I("ENET0_MDIO_I"), ENET0_EXT_INTIN("ENET0_EXT_INTIN"), ENET0_GMII_RXD("ENET0_GMII_RXD"), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), TTC0_WAVE0_OUT("TTC0_WAVE0_OUT"), TTC0_WAVE1_OUT("TTC0_WAVE1_OUT"), TTC0_WAVE2_OUT("TTC0_WAVE2_OUT"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), S_AXI_HP0_ARREADY("S_AXI_HP0_ARREADY"), S_AXI_HP0_AWREADY("S_AXI_HP0_AWREADY"), S_AXI_HP0_BVALID("S_AXI_HP0_BVALID"), S_AXI_HP0_RLAST("S_AXI_HP0_RLAST"), S_AXI_HP0_RVALID("S_AXI_HP0_RVALID"), S_AXI_HP0_WREADY("S_AXI_HP0_WREADY"), S_AXI_HP0_BRESP("S_AXI_HP0_BRESP"), S_AXI_HP0_RRESP("S_AXI_HP0_RRESP"), S_AXI_HP0_BID("S_AXI_HP0_BID"), S_AXI_HP0_RID("S_AXI_HP0_RID"), S_AXI_HP0_RDATA("S_AXI_HP0_RDATA"), S_AXI_HP0_RCOUNT("S_AXI_HP0_RCOUNT"), S_AXI_HP0_WCOUNT("S_AXI_HP0_WCOUNT"), S_AXI_HP0_RACOUNT("S_AXI_HP0_RACOUNT"), S_AXI_HP0_WACOUNT("S_AXI_HP0_WACOUNT"), S_AXI_HP0_ACLK("S_AXI_HP0_ACLK"), S_AXI_HP0_ARVALID("S_AXI_HP0_ARVALID"), S_AXI_HP0_AWVALID("S_AXI_HP0_AWVALID"), S_AXI_HP0_BREADY("S_AXI_HP0_BREADY"), S_AXI_HP0_RDISSUECAP1_EN("S_AXI_HP0_RDISSUECAP1_EN"), S_AXI_HP0_RREADY("S_AXI_HP0_RREADY"), S_AXI_HP0_WLAST("S_AXI_HP0_WLAST"), S_AXI_HP0_WRISSUECAP1_EN("S_AXI_HP0_WRISSUECAP1_EN"), S_AXI_HP0_WVALID("S_AXI_HP0_WVALID"), S_AXI_HP0_ARBURST("S_AXI_HP0_ARBURST"), S_AXI_HP0_ARLOCK("S_AXI_HP0_ARLOCK"), S_AXI_HP0_ARSIZE("S_AXI_HP0_ARSIZE"), S_AXI_HP0_AWBURST("S_AXI_HP0_AWBURST"), S_AXI_HP0_AWLOCK("S_AXI_HP0_AWLOCK"), S_AXI_HP0_AWSIZE("S_AXI_HP0_AWSIZE"), S_AXI_HP0_ARPROT("S_AXI_HP0_ARPROT"), S_AXI_HP0_AWPROT("S_AXI_HP0_AWPROT"), S_AXI_HP0_ARADDR("S_AXI_HP0_ARADDR"), S_AXI_HP0_AWADDR("S_AXI_HP0_AWADDR"), S_AXI_HP0_ARCACHE("S_AXI_HP0_ARCACHE"), S_AXI_HP0_ARLEN("S_AXI_HP0_ARLEN"), S_AXI_HP0_ARQOS("S_AXI_HP0_ARQOS"), S_AXI_HP0_AWCACHE("S_AXI_HP0_AWCACHE"), S_AXI_HP0_AWLEN("S_AXI_HP0_AWLEN"), S_AXI_HP0_AWQOS("S_AXI_HP0_AWQOS"), S_AXI_HP0_ARID("S_AXI_HP0_ARID"), S_AXI_HP0_AWID("S_AXI_HP0_AWID"), S_AXI_HP0_WID("S_AXI_HP0_WID"), S_AXI_HP0_WDATA("S_AXI_HP0_WDATA"), S_AXI_HP0_WSTRB("S_AXI_HP0_WSTRB"), IRQ_F2P("IRQ_F2P"), FCLK_CLK0("FCLK_CLK0"), FCLK_CLK1("FCLK_CLK1"), FCLK_CLK2("FCLK_CLK2"), FCLK_CLK3("FCLK_CLK3"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
366 {
367 
368  // initialize pins
369  mp_impl->ENET0_GMII_TX_EN(ENET0_GMII_TX_EN);
370  mp_impl->ENET0_GMII_TX_ER(ENET0_GMII_TX_ER);
371  mp_impl->ENET0_MDIO_MDC(ENET0_MDIO_MDC);
372  mp_impl->ENET0_MDIO_O(ENET0_MDIO_O);
373  mp_impl->ENET0_MDIO_T(ENET0_MDIO_T);
374  mp_impl->ENET0_GMII_TXD(ENET0_GMII_TXD);
375  mp_impl->ENET0_GMII_COL(ENET0_GMII_COL);
376  mp_impl->ENET0_GMII_CRS(ENET0_GMII_CRS);
377  mp_impl->ENET0_GMII_RX_CLK(ENET0_GMII_RX_CLK);
378  mp_impl->ENET0_GMII_RX_DV(ENET0_GMII_RX_DV);
379  mp_impl->ENET0_GMII_RX_ER(ENET0_GMII_RX_ER);
380  mp_impl->ENET0_GMII_TX_CLK(ENET0_GMII_TX_CLK);
381  mp_impl->ENET0_MDIO_I(ENET0_MDIO_I);
382  mp_impl->ENET0_EXT_INTIN(ENET0_EXT_INTIN);
383  mp_impl->ENET0_GMII_RXD(ENET0_GMII_RXD);
384  mp_impl->GPIO_I(GPIO_I);
385  mp_impl->GPIO_O(GPIO_O);
386  mp_impl->GPIO_T(GPIO_T);
387  mp_impl->TTC0_WAVE0_OUT(TTC0_WAVE0_OUT);
388  mp_impl->TTC0_WAVE1_OUT(TTC0_WAVE1_OUT);
389  mp_impl->TTC0_WAVE2_OUT(TTC0_WAVE2_OUT);
390  mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
391  mp_impl->S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT);
392  mp_impl->S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT);
393  mp_impl->S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT);
394  mp_impl->S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT);
395  mp_impl->S_AXI_HP0_ACLK(S_AXI_HP0_ACLK);
396  mp_impl->S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN);
397  mp_impl->S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN);
398  mp_impl->IRQ_F2P(IRQ_F2P);
399  mp_impl->FCLK_CLK0(FCLK_CLK0);
400  mp_impl->FCLK_CLK1(FCLK_CLK1);
401  mp_impl->FCLK_CLK2(FCLK_CLK2);
402  mp_impl->FCLK_CLK3(FCLK_CLK3);
403  mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
404  mp_impl->MIO(MIO);
405  mp_impl->DDR_CAS_n(DDR_CAS_n);
406  mp_impl->DDR_CKE(DDR_CKE);
407  mp_impl->DDR_Clk_n(DDR_Clk_n);
408  mp_impl->DDR_Clk(DDR_Clk);
409  mp_impl->DDR_CS_n(DDR_CS_n);
410  mp_impl->DDR_DRSTB(DDR_DRSTB);
411  mp_impl->DDR_ODT(DDR_ODT);
412  mp_impl->DDR_RAS_n(DDR_RAS_n);
413  mp_impl->DDR_WEB(DDR_WEB);
414  mp_impl->DDR_BankAddr(DDR_BankAddr);
415  mp_impl->DDR_Addr(DDR_Addr);
416  mp_impl->DDR_VRN(DDR_VRN);
417  mp_impl->DDR_VRP(DDR_VRP);
418  mp_impl->DDR_DM(DDR_DM);
419  mp_impl->DDR_DQ(DDR_DQ);
420  mp_impl->DDR_DQS_n(DDR_DQS_n);
421  mp_impl->DDR_DQS(DDR_DQS);
422  mp_impl->PS_SRSTB(PS_SRSTB);
423  mp_impl->PS_CLK(PS_CLK);
424  mp_impl->PS_PORB(PS_PORB);
425 
426  // initialize transactors
427  mp_M_AXI_GP0_transactor = NULL;
428  mp_M_AXI_GP0_ARLOCK_converter = NULL;
429  mp_M_AXI_GP0_AWLOCK_converter = NULL;
430  mp_M_AXI_GP0_ARLEN_converter = NULL;
431  mp_M_AXI_GP0_AWLEN_converter = NULL;
432  mp_S_AXI_HP0_transactor = NULL;
433  mp_S_AXI_HP0_ARLOCK_converter = NULL;
434  mp_S_AXI_HP0_AWLOCK_converter = NULL;
435  mp_S_AXI_HP0_ARLEN_converter = NULL;
436  mp_S_AXI_HP0_AWLEN_converter = NULL;
437 
438  // initialize socket stubs
439 
440 }
441 
442 void design_1_processing_system7_0_0::before_end_of_elaboration()
443 {
444  // configure 'M_AXI_GP0' transactor
445 
446  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
447  {
448  // Instantiate Socket Stubs
449 
450  // 'M_AXI_GP0' transactor parameters
451  xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
452  M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
453  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
454  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
455  M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
456  M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
457  M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
458  M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
459  M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
460  M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
461  M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
462  M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
463  M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
464  M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
465  M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
466  M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
467  M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
468  M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
469  M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
470  M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
471  M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
472  M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
473  M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
474  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
475  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
476  M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
477  M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
478  M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
479  M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
480  M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.000");
481  M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
482  M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
483  M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
484 
485  mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
486 
487  // M_AXI_GP0' transactor ports
488 
489  mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
490  mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
491  mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
492  mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
493  mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
494  mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
495  mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
496  mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
497  mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
498  mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
499  mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
500  mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
501  mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
502  mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
503  mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
504  mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
505  mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
506  mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
507  mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
508  mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
509  mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
510  mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
511  mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
512  mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
513  mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
514  mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
515  mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
516  mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
517  mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
518  mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
519  mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
520  mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
521  mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
522  mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
523  mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
524  mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
525  mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
526  mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
527  mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
528  mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
529  mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
530  mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
531  mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
532  mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
533  mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
534  mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
535  mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
536  mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
537  mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
538  mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
539  m_M_AXI_GP0_transactor_rst_signal.write(1);
540  mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
541 
542  // M_AXI_GP0' transactor sockets
543 
544  mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
545  mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
546  }
547  else
548  {
549  }
550 
551  // configure 'S_AXI_HP0' transactor
552 
553  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
554  {
555  // Instantiate Socket Stubs
556 
557  // 'S_AXI_HP0' transactor parameters
558  xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
559  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
560  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
561  S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "64");
562  S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
563  S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
564  S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
565  S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
566  S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
567  S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
568  S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
569  S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
570  S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
571  S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
572  S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
573  S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
574  S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
575  S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
576  S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
577  S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
578  S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
579  S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
580  S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
581  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
582  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
583  S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
584  S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
585  S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
586  S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
587  S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.000");
588  S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
589  S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
590  S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
591 
592  mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
593 
594  // S_AXI_HP0' transactor ports
595 
596  mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
597  mp_S_AXI_HP0_transactor->AWREADY(S_AXI_HP0_AWREADY);
598  mp_S_AXI_HP0_transactor->BVALID(S_AXI_HP0_BVALID);
599  mp_S_AXI_HP0_transactor->RLAST(S_AXI_HP0_RLAST);
600  mp_S_AXI_HP0_transactor->RVALID(S_AXI_HP0_RVALID);
601  mp_S_AXI_HP0_transactor->WREADY(S_AXI_HP0_WREADY);
602  mp_S_AXI_HP0_transactor->BRESP(S_AXI_HP0_BRESP);
603  mp_S_AXI_HP0_transactor->RRESP(S_AXI_HP0_RRESP);
604  mp_S_AXI_HP0_transactor->BID(S_AXI_HP0_BID);
605  mp_S_AXI_HP0_transactor->RID(S_AXI_HP0_RID);
606  mp_S_AXI_HP0_transactor->RDATA(S_AXI_HP0_RDATA);
607  mp_S_AXI_HP0_transactor->ARVALID(S_AXI_HP0_ARVALID);
608  mp_S_AXI_HP0_transactor->AWVALID(S_AXI_HP0_AWVALID);
609  mp_S_AXI_HP0_transactor->BREADY(S_AXI_HP0_BREADY);
610  mp_S_AXI_HP0_transactor->RREADY(S_AXI_HP0_RREADY);
611  mp_S_AXI_HP0_transactor->WLAST(S_AXI_HP0_WLAST);
612  mp_S_AXI_HP0_transactor->WVALID(S_AXI_HP0_WVALID);
613  mp_S_AXI_HP0_transactor->ARBURST(S_AXI_HP0_ARBURST);
614  mp_S_AXI_HP0_ARLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_ARLOCK_converter");
615  mp_S_AXI_HP0_ARLOCK_converter->vector_in(S_AXI_HP0_ARLOCK);
616  mp_S_AXI_HP0_ARLOCK_converter->scalar_out(m_S_AXI_HP0_ARLOCK_converter_signal);
617  mp_S_AXI_HP0_transactor->ARLOCK(m_S_AXI_HP0_ARLOCK_converter_signal);
618  mp_S_AXI_HP0_transactor->ARSIZE(S_AXI_HP0_ARSIZE);
619  mp_S_AXI_HP0_transactor->AWBURST(S_AXI_HP0_AWBURST);
620  mp_S_AXI_HP0_AWLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_AWLOCK_converter");
621  mp_S_AXI_HP0_AWLOCK_converter->vector_in(S_AXI_HP0_AWLOCK);
622  mp_S_AXI_HP0_AWLOCK_converter->scalar_out(m_S_AXI_HP0_AWLOCK_converter_signal);
623  mp_S_AXI_HP0_transactor->AWLOCK(m_S_AXI_HP0_AWLOCK_converter_signal);
624  mp_S_AXI_HP0_transactor->AWSIZE(S_AXI_HP0_AWSIZE);
625  mp_S_AXI_HP0_transactor->ARPROT(S_AXI_HP0_ARPROT);
626  mp_S_AXI_HP0_transactor->AWPROT(S_AXI_HP0_AWPROT);
627  mp_S_AXI_HP0_transactor->ARADDR(S_AXI_HP0_ARADDR);
628  mp_S_AXI_HP0_transactor->AWADDR(S_AXI_HP0_AWADDR);
629  mp_S_AXI_HP0_transactor->ARCACHE(S_AXI_HP0_ARCACHE);
630  mp_S_AXI_HP0_ARLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_ARLEN_converter");
631  mp_S_AXI_HP0_ARLEN_converter->vector_in(S_AXI_HP0_ARLEN);
632  mp_S_AXI_HP0_ARLEN_converter->vector_out(m_S_AXI_HP0_ARLEN_converter_signal);
633  mp_S_AXI_HP0_transactor->ARLEN(m_S_AXI_HP0_ARLEN_converter_signal);
634  mp_S_AXI_HP0_transactor->ARQOS(S_AXI_HP0_ARQOS);
635  mp_S_AXI_HP0_transactor->AWCACHE(S_AXI_HP0_AWCACHE);
636  mp_S_AXI_HP0_AWLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_AWLEN_converter");
637  mp_S_AXI_HP0_AWLEN_converter->vector_in(S_AXI_HP0_AWLEN);
638  mp_S_AXI_HP0_AWLEN_converter->vector_out(m_S_AXI_HP0_AWLEN_converter_signal);
639  mp_S_AXI_HP0_transactor->AWLEN(m_S_AXI_HP0_AWLEN_converter_signal);
640  mp_S_AXI_HP0_transactor->AWQOS(S_AXI_HP0_AWQOS);
641  mp_S_AXI_HP0_transactor->ARID(S_AXI_HP0_ARID);
642  mp_S_AXI_HP0_transactor->AWID(S_AXI_HP0_AWID);
643  mp_S_AXI_HP0_transactor->WDATA(S_AXI_HP0_WDATA);
644  mp_S_AXI_HP0_transactor->WSTRB(S_AXI_HP0_WSTRB);
645  mp_S_AXI_HP0_transactor->CLK(S_AXI_HP0_ACLK);
646  m_S_AXI_HP0_transactor_rst_signal.write(1);
647  mp_S_AXI_HP0_transactor->RST(m_S_AXI_HP0_transactor_rst_signal);
648 
649  // S_AXI_HP0' transactor sockets
650 
651  mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
652  mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
653  }
654  else
655  {
656  }
657 
658 }
659 
660 #endif // XM_SYSTEMC
661 
662 
663 
664 
665 #ifdef RIVIERA
666 design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), ENET0_GMII_TX_EN("ENET0_GMII_TX_EN"), ENET0_GMII_TX_ER("ENET0_GMII_TX_ER"), ENET0_MDIO_MDC("ENET0_MDIO_MDC"), ENET0_MDIO_O("ENET0_MDIO_O"), ENET0_MDIO_T("ENET0_MDIO_T"), ENET0_GMII_TXD("ENET0_GMII_TXD"), ENET0_GMII_COL("ENET0_GMII_COL"), ENET0_GMII_CRS("ENET0_GMII_CRS"), ENET0_GMII_RX_CLK("ENET0_GMII_RX_CLK"), ENET0_GMII_RX_DV("ENET0_GMII_RX_DV"), ENET0_GMII_RX_ER("ENET0_GMII_RX_ER"), ENET0_GMII_TX_CLK("ENET0_GMII_TX_CLK"), ENET0_MDIO_I("ENET0_MDIO_I"), ENET0_EXT_INTIN("ENET0_EXT_INTIN"), ENET0_GMII_RXD("ENET0_GMII_RXD"), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), TTC0_WAVE0_OUT("TTC0_WAVE0_OUT"), TTC0_WAVE1_OUT("TTC0_WAVE1_OUT"), TTC0_WAVE2_OUT("TTC0_WAVE2_OUT"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), S_AXI_HP0_ARREADY("S_AXI_HP0_ARREADY"), S_AXI_HP0_AWREADY("S_AXI_HP0_AWREADY"), S_AXI_HP0_BVALID("S_AXI_HP0_BVALID"), S_AXI_HP0_RLAST("S_AXI_HP0_RLAST"), S_AXI_HP0_RVALID("S_AXI_HP0_RVALID"), S_AXI_HP0_WREADY("S_AXI_HP0_WREADY"), S_AXI_HP0_BRESP("S_AXI_HP0_BRESP"), S_AXI_HP0_RRESP("S_AXI_HP0_RRESP"), S_AXI_HP0_BID("S_AXI_HP0_BID"), S_AXI_HP0_RID("S_AXI_HP0_RID"), S_AXI_HP0_RDATA("S_AXI_HP0_RDATA"), S_AXI_HP0_RCOUNT("S_AXI_HP0_RCOUNT"), S_AXI_HP0_WCOUNT("S_AXI_HP0_WCOUNT"), S_AXI_HP0_RACOUNT("S_AXI_HP0_RACOUNT"), S_AXI_HP0_WACOUNT("S_AXI_HP0_WACOUNT"), S_AXI_HP0_ACLK("S_AXI_HP0_ACLK"), S_AXI_HP0_ARVALID("S_AXI_HP0_ARVALID"), S_AXI_HP0_AWVALID("S_AXI_HP0_AWVALID"), S_AXI_HP0_BREADY("S_AXI_HP0_BREADY"), S_AXI_HP0_RDISSUECAP1_EN("S_AXI_HP0_RDISSUECAP1_EN"), S_AXI_HP0_RREADY("S_AXI_HP0_RREADY"), S_AXI_HP0_WLAST("S_AXI_HP0_WLAST"), S_AXI_HP0_WRISSUECAP1_EN("S_AXI_HP0_WRISSUECAP1_EN"), S_AXI_HP0_WVALID("S_AXI_HP0_WVALID"), S_AXI_HP0_ARBURST("S_AXI_HP0_ARBURST"), S_AXI_HP0_ARLOCK("S_AXI_HP0_ARLOCK"), S_AXI_HP0_ARSIZE("S_AXI_HP0_ARSIZE"), S_AXI_HP0_AWBURST("S_AXI_HP0_AWBURST"), S_AXI_HP0_AWLOCK("S_AXI_HP0_AWLOCK"), S_AXI_HP0_AWSIZE("S_AXI_HP0_AWSIZE"), S_AXI_HP0_ARPROT("S_AXI_HP0_ARPROT"), S_AXI_HP0_AWPROT("S_AXI_HP0_AWPROT"), S_AXI_HP0_ARADDR("S_AXI_HP0_ARADDR"), S_AXI_HP0_AWADDR("S_AXI_HP0_AWADDR"), S_AXI_HP0_ARCACHE("S_AXI_HP0_ARCACHE"), S_AXI_HP0_ARLEN("S_AXI_HP0_ARLEN"), S_AXI_HP0_ARQOS("S_AXI_HP0_ARQOS"), S_AXI_HP0_AWCACHE("S_AXI_HP0_AWCACHE"), S_AXI_HP0_AWLEN("S_AXI_HP0_AWLEN"), S_AXI_HP0_AWQOS("S_AXI_HP0_AWQOS"), S_AXI_HP0_ARID("S_AXI_HP0_ARID"), S_AXI_HP0_AWID("S_AXI_HP0_AWID"), S_AXI_HP0_WID("S_AXI_HP0_WID"), S_AXI_HP0_WDATA("S_AXI_HP0_WDATA"), S_AXI_HP0_WSTRB("S_AXI_HP0_WSTRB"), IRQ_F2P("IRQ_F2P"), FCLK_CLK0("FCLK_CLK0"), FCLK_CLK1("FCLK_CLK1"), FCLK_CLK2("FCLK_CLK2"), FCLK_CLK3("FCLK_CLK3"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
667 {
668 
669  // initialize pins
670  mp_impl->ENET0_GMII_TX_EN(ENET0_GMII_TX_EN);
671  mp_impl->ENET0_GMII_TX_ER(ENET0_GMII_TX_ER);
672  mp_impl->ENET0_MDIO_MDC(ENET0_MDIO_MDC);
673  mp_impl->ENET0_MDIO_O(ENET0_MDIO_O);
674  mp_impl->ENET0_MDIO_T(ENET0_MDIO_T);
675  mp_impl->ENET0_GMII_TXD(ENET0_GMII_TXD);
676  mp_impl->ENET0_GMII_COL(ENET0_GMII_COL);
677  mp_impl->ENET0_GMII_CRS(ENET0_GMII_CRS);
678  mp_impl->ENET0_GMII_RX_CLK(ENET0_GMII_RX_CLK);
679  mp_impl->ENET0_GMII_RX_DV(ENET0_GMII_RX_DV);
680  mp_impl->ENET0_GMII_RX_ER(ENET0_GMII_RX_ER);
681  mp_impl->ENET0_GMII_TX_CLK(ENET0_GMII_TX_CLK);
682  mp_impl->ENET0_MDIO_I(ENET0_MDIO_I);
683  mp_impl->ENET0_EXT_INTIN(ENET0_EXT_INTIN);
684  mp_impl->ENET0_GMII_RXD(ENET0_GMII_RXD);
685  mp_impl->GPIO_I(GPIO_I);
686  mp_impl->GPIO_O(GPIO_O);
687  mp_impl->GPIO_T(GPIO_T);
688  mp_impl->TTC0_WAVE0_OUT(TTC0_WAVE0_OUT);
689  mp_impl->TTC0_WAVE1_OUT(TTC0_WAVE1_OUT);
690  mp_impl->TTC0_WAVE2_OUT(TTC0_WAVE2_OUT);
691  mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
692  mp_impl->S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT);
693  mp_impl->S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT);
694  mp_impl->S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT);
695  mp_impl->S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT);
696  mp_impl->S_AXI_HP0_ACLK(S_AXI_HP0_ACLK);
697  mp_impl->S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN);
698  mp_impl->S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN);
699  mp_impl->IRQ_F2P(IRQ_F2P);
700  mp_impl->FCLK_CLK0(FCLK_CLK0);
701  mp_impl->FCLK_CLK1(FCLK_CLK1);
702  mp_impl->FCLK_CLK2(FCLK_CLK2);
703  mp_impl->FCLK_CLK3(FCLK_CLK3);
704  mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
705  mp_impl->MIO(MIO);
706  mp_impl->DDR_CAS_n(DDR_CAS_n);
707  mp_impl->DDR_CKE(DDR_CKE);
708  mp_impl->DDR_Clk_n(DDR_Clk_n);
709  mp_impl->DDR_Clk(DDR_Clk);
710  mp_impl->DDR_CS_n(DDR_CS_n);
711  mp_impl->DDR_DRSTB(DDR_DRSTB);
712  mp_impl->DDR_ODT(DDR_ODT);
713  mp_impl->DDR_RAS_n(DDR_RAS_n);
714  mp_impl->DDR_WEB(DDR_WEB);
715  mp_impl->DDR_BankAddr(DDR_BankAddr);
716  mp_impl->DDR_Addr(DDR_Addr);
717  mp_impl->DDR_VRN(DDR_VRN);
718  mp_impl->DDR_VRP(DDR_VRP);
719  mp_impl->DDR_DM(DDR_DM);
720  mp_impl->DDR_DQ(DDR_DQ);
721  mp_impl->DDR_DQS_n(DDR_DQS_n);
722  mp_impl->DDR_DQS(DDR_DQS);
723  mp_impl->PS_SRSTB(PS_SRSTB);
724  mp_impl->PS_CLK(PS_CLK);
725  mp_impl->PS_PORB(PS_PORB);
726 
727  // initialize transactors
728  mp_M_AXI_GP0_transactor = NULL;
729  mp_M_AXI_GP0_ARLOCK_converter = NULL;
730  mp_M_AXI_GP0_AWLOCK_converter = NULL;
731  mp_M_AXI_GP0_ARLEN_converter = NULL;
732  mp_M_AXI_GP0_AWLEN_converter = NULL;
733  mp_S_AXI_HP0_transactor = NULL;
734  mp_S_AXI_HP0_ARLOCK_converter = NULL;
735  mp_S_AXI_HP0_AWLOCK_converter = NULL;
736  mp_S_AXI_HP0_ARLEN_converter = NULL;
737  mp_S_AXI_HP0_AWLEN_converter = NULL;
738 
739  // initialize socket stubs
740 
741 }
742 
743 void design_1_processing_system7_0_0::before_end_of_elaboration()
744 {
745  // configure 'M_AXI_GP0' transactor
746 
747  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
748  {
749  // Instantiate Socket Stubs
750 
751  // 'M_AXI_GP0' transactor parameters
752  xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
753  M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
754  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
755  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
756  M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
757  M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
758  M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
759  M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
760  M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
761  M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
762  M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
763  M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
764  M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
765  M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
766  M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
767  M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
768  M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
769  M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
770  M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
771  M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
772  M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
773  M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
774  M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
775  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
776  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
777  M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
778  M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
779  M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
780  M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
781  M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.000");
782  M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
783  M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
784  M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
785 
786  mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
787 
788  // M_AXI_GP0' transactor ports
789 
790  mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
791  mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
792  mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
793  mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
794  mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
795  mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
796  mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
797  mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
798  mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
799  mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
800  mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
801  mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
802  mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
803  mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
804  mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
805  mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
806  mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
807  mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
808  mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
809  mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
810  mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
811  mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
812  mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
813  mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
814  mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
815  mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
816  mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
817  mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
818  mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
819  mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
820  mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
821  mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
822  mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
823  mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
824  mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
825  mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
826  mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
827  mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
828  mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
829  mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
830  mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
831  mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
832  mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
833  mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
834  mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
835  mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
836  mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
837  mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
838  mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
839  mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
840  m_M_AXI_GP0_transactor_rst_signal.write(1);
841  mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
842 
843  // M_AXI_GP0' transactor sockets
844 
845  mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
846  mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
847  }
848  else
849  {
850  }
851 
852  // configure 'S_AXI_HP0' transactor
853 
854  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
855  {
856  // Instantiate Socket Stubs
857 
858  // 'S_AXI_HP0' transactor parameters
859  xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
860  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
861  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
862  S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "64");
863  S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
864  S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
865  S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
866  S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
867  S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
868  S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
869  S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
870  S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
871  S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
872  S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
873  S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
874  S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
875  S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
876  S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
877  S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
878  S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
879  S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
880  S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
881  S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
882  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
883  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
884  S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
885  S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
886  S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
887  S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
888  S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.000");
889  S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
890  S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
891  S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
892 
893  mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
894 
895  // S_AXI_HP0' transactor ports
896 
897  mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
898  mp_S_AXI_HP0_transactor->AWREADY(S_AXI_HP0_AWREADY);
899  mp_S_AXI_HP0_transactor->BVALID(S_AXI_HP0_BVALID);
900  mp_S_AXI_HP0_transactor->RLAST(S_AXI_HP0_RLAST);
901  mp_S_AXI_HP0_transactor->RVALID(S_AXI_HP0_RVALID);
902  mp_S_AXI_HP0_transactor->WREADY(S_AXI_HP0_WREADY);
903  mp_S_AXI_HP0_transactor->BRESP(S_AXI_HP0_BRESP);
904  mp_S_AXI_HP0_transactor->RRESP(S_AXI_HP0_RRESP);
905  mp_S_AXI_HP0_transactor->BID(S_AXI_HP0_BID);
906  mp_S_AXI_HP0_transactor->RID(S_AXI_HP0_RID);
907  mp_S_AXI_HP0_transactor->RDATA(S_AXI_HP0_RDATA);
908  mp_S_AXI_HP0_transactor->ARVALID(S_AXI_HP0_ARVALID);
909  mp_S_AXI_HP0_transactor->AWVALID(S_AXI_HP0_AWVALID);
910  mp_S_AXI_HP0_transactor->BREADY(S_AXI_HP0_BREADY);
911  mp_S_AXI_HP0_transactor->RREADY(S_AXI_HP0_RREADY);
912  mp_S_AXI_HP0_transactor->WLAST(S_AXI_HP0_WLAST);
913  mp_S_AXI_HP0_transactor->WVALID(S_AXI_HP0_WVALID);
914  mp_S_AXI_HP0_transactor->ARBURST(S_AXI_HP0_ARBURST);
915  mp_S_AXI_HP0_ARLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_ARLOCK_converter");
916  mp_S_AXI_HP0_ARLOCK_converter->vector_in(S_AXI_HP0_ARLOCK);
917  mp_S_AXI_HP0_ARLOCK_converter->scalar_out(m_S_AXI_HP0_ARLOCK_converter_signal);
918  mp_S_AXI_HP0_transactor->ARLOCK(m_S_AXI_HP0_ARLOCK_converter_signal);
919  mp_S_AXI_HP0_transactor->ARSIZE(S_AXI_HP0_ARSIZE);
920  mp_S_AXI_HP0_transactor->AWBURST(S_AXI_HP0_AWBURST);
921  mp_S_AXI_HP0_AWLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_AWLOCK_converter");
922  mp_S_AXI_HP0_AWLOCK_converter->vector_in(S_AXI_HP0_AWLOCK);
923  mp_S_AXI_HP0_AWLOCK_converter->scalar_out(m_S_AXI_HP0_AWLOCK_converter_signal);
924  mp_S_AXI_HP0_transactor->AWLOCK(m_S_AXI_HP0_AWLOCK_converter_signal);
925  mp_S_AXI_HP0_transactor->AWSIZE(S_AXI_HP0_AWSIZE);
926  mp_S_AXI_HP0_transactor->ARPROT(S_AXI_HP0_ARPROT);
927  mp_S_AXI_HP0_transactor->AWPROT(S_AXI_HP0_AWPROT);
928  mp_S_AXI_HP0_transactor->ARADDR(S_AXI_HP0_ARADDR);
929  mp_S_AXI_HP0_transactor->AWADDR(S_AXI_HP0_AWADDR);
930  mp_S_AXI_HP0_transactor->ARCACHE(S_AXI_HP0_ARCACHE);
931  mp_S_AXI_HP0_ARLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_ARLEN_converter");
932  mp_S_AXI_HP0_ARLEN_converter->vector_in(S_AXI_HP0_ARLEN);
933  mp_S_AXI_HP0_ARLEN_converter->vector_out(m_S_AXI_HP0_ARLEN_converter_signal);
934  mp_S_AXI_HP0_transactor->ARLEN(m_S_AXI_HP0_ARLEN_converter_signal);
935  mp_S_AXI_HP0_transactor->ARQOS(S_AXI_HP0_ARQOS);
936  mp_S_AXI_HP0_transactor->AWCACHE(S_AXI_HP0_AWCACHE);
937  mp_S_AXI_HP0_AWLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_AWLEN_converter");
938  mp_S_AXI_HP0_AWLEN_converter->vector_in(S_AXI_HP0_AWLEN);
939  mp_S_AXI_HP0_AWLEN_converter->vector_out(m_S_AXI_HP0_AWLEN_converter_signal);
940  mp_S_AXI_HP0_transactor->AWLEN(m_S_AXI_HP0_AWLEN_converter_signal);
941  mp_S_AXI_HP0_transactor->AWQOS(S_AXI_HP0_AWQOS);
942  mp_S_AXI_HP0_transactor->ARID(S_AXI_HP0_ARID);
943  mp_S_AXI_HP0_transactor->AWID(S_AXI_HP0_AWID);
944  mp_S_AXI_HP0_transactor->WDATA(S_AXI_HP0_WDATA);
945  mp_S_AXI_HP0_transactor->WSTRB(S_AXI_HP0_WSTRB);
946  mp_S_AXI_HP0_transactor->CLK(S_AXI_HP0_ACLK);
947  m_S_AXI_HP0_transactor_rst_signal.write(1);
948  mp_S_AXI_HP0_transactor->RST(m_S_AXI_HP0_transactor_rst_signal);
949 
950  // S_AXI_HP0' transactor sockets
951 
952  mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
953  mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
954  }
955  else
956  {
957  }
958 
959 }
960 
961 #endif // RIVIERA
962 
963 
964 
965 
966 #ifdef VCSSYSTEMC
967 design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), ENET0_GMII_TX_EN("ENET0_GMII_TX_EN"), ENET0_GMII_TX_ER("ENET0_GMII_TX_ER"), ENET0_MDIO_MDC("ENET0_MDIO_MDC"), ENET0_MDIO_O("ENET0_MDIO_O"), ENET0_MDIO_T("ENET0_MDIO_T"), ENET0_GMII_TXD("ENET0_GMII_TXD"), ENET0_GMII_COL("ENET0_GMII_COL"), ENET0_GMII_CRS("ENET0_GMII_CRS"), ENET0_GMII_RX_CLK("ENET0_GMII_RX_CLK"), ENET0_GMII_RX_DV("ENET0_GMII_RX_DV"), ENET0_GMII_RX_ER("ENET0_GMII_RX_ER"), ENET0_GMII_TX_CLK("ENET0_GMII_TX_CLK"), ENET0_MDIO_I("ENET0_MDIO_I"), ENET0_EXT_INTIN("ENET0_EXT_INTIN"), ENET0_GMII_RXD("ENET0_GMII_RXD"), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), TTC0_WAVE0_OUT("TTC0_WAVE0_OUT"), TTC0_WAVE1_OUT("TTC0_WAVE1_OUT"), TTC0_WAVE2_OUT("TTC0_WAVE2_OUT"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), S_AXI_HP0_ARREADY("S_AXI_HP0_ARREADY"), S_AXI_HP0_AWREADY("S_AXI_HP0_AWREADY"), S_AXI_HP0_BVALID("S_AXI_HP0_BVALID"), S_AXI_HP0_RLAST("S_AXI_HP0_RLAST"), S_AXI_HP0_RVALID("S_AXI_HP0_RVALID"), S_AXI_HP0_WREADY("S_AXI_HP0_WREADY"), S_AXI_HP0_BRESP("S_AXI_HP0_BRESP"), S_AXI_HP0_RRESP("S_AXI_HP0_RRESP"), S_AXI_HP0_BID("S_AXI_HP0_BID"), S_AXI_HP0_RID("S_AXI_HP0_RID"), S_AXI_HP0_RDATA("S_AXI_HP0_RDATA"), S_AXI_HP0_RCOUNT("S_AXI_HP0_RCOUNT"), S_AXI_HP0_WCOUNT("S_AXI_HP0_WCOUNT"), S_AXI_HP0_RACOUNT("S_AXI_HP0_RACOUNT"), S_AXI_HP0_WACOUNT("S_AXI_HP0_WACOUNT"), S_AXI_HP0_ACLK("S_AXI_HP0_ACLK"), S_AXI_HP0_ARVALID("S_AXI_HP0_ARVALID"), S_AXI_HP0_AWVALID("S_AXI_HP0_AWVALID"), S_AXI_HP0_BREADY("S_AXI_HP0_BREADY"), S_AXI_HP0_RDISSUECAP1_EN("S_AXI_HP0_RDISSUECAP1_EN"), S_AXI_HP0_RREADY("S_AXI_HP0_RREADY"), S_AXI_HP0_WLAST("S_AXI_HP0_WLAST"), S_AXI_HP0_WRISSUECAP1_EN("S_AXI_HP0_WRISSUECAP1_EN"), S_AXI_HP0_WVALID("S_AXI_HP0_WVALID"), S_AXI_HP0_ARBURST("S_AXI_HP0_ARBURST"), S_AXI_HP0_ARLOCK("S_AXI_HP0_ARLOCK"), S_AXI_HP0_ARSIZE("S_AXI_HP0_ARSIZE"), S_AXI_HP0_AWBURST("S_AXI_HP0_AWBURST"), S_AXI_HP0_AWLOCK("S_AXI_HP0_AWLOCK"), S_AXI_HP0_AWSIZE("S_AXI_HP0_AWSIZE"), S_AXI_HP0_ARPROT("S_AXI_HP0_ARPROT"), S_AXI_HP0_AWPROT("S_AXI_HP0_AWPROT"), S_AXI_HP0_ARADDR("S_AXI_HP0_ARADDR"), S_AXI_HP0_AWADDR("S_AXI_HP0_AWADDR"), S_AXI_HP0_ARCACHE("S_AXI_HP0_ARCACHE"), S_AXI_HP0_ARLEN("S_AXI_HP0_ARLEN"), S_AXI_HP0_ARQOS("S_AXI_HP0_ARQOS"), S_AXI_HP0_AWCACHE("S_AXI_HP0_AWCACHE"), S_AXI_HP0_AWLEN("S_AXI_HP0_AWLEN"), S_AXI_HP0_AWQOS("S_AXI_HP0_AWQOS"), S_AXI_HP0_ARID("S_AXI_HP0_ARID"), S_AXI_HP0_AWID("S_AXI_HP0_AWID"), S_AXI_HP0_WID("S_AXI_HP0_WID"), S_AXI_HP0_WDATA("S_AXI_HP0_WDATA"), S_AXI_HP0_WSTRB("S_AXI_HP0_WSTRB"), IRQ_F2P("IRQ_F2P"), FCLK_CLK0("FCLK_CLK0"), FCLK_CLK1("FCLK_CLK1"), FCLK_CLK2("FCLK_CLK2"), FCLK_CLK3("FCLK_CLK3"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
968 {
969  // initialize pins
970  mp_impl->ENET0_GMII_TX_EN(ENET0_GMII_TX_EN);
971  mp_impl->ENET0_GMII_TX_ER(ENET0_GMII_TX_ER);
972  mp_impl->ENET0_MDIO_MDC(ENET0_MDIO_MDC);
973  mp_impl->ENET0_MDIO_O(ENET0_MDIO_O);
974  mp_impl->ENET0_MDIO_T(ENET0_MDIO_T);
975  mp_impl->ENET0_GMII_TXD(ENET0_GMII_TXD);
976  mp_impl->ENET0_GMII_COL(ENET0_GMII_COL);
977  mp_impl->ENET0_GMII_CRS(ENET0_GMII_CRS);
978  mp_impl->ENET0_GMII_RX_CLK(ENET0_GMII_RX_CLK);
979  mp_impl->ENET0_GMII_RX_DV(ENET0_GMII_RX_DV);
980  mp_impl->ENET0_GMII_RX_ER(ENET0_GMII_RX_ER);
981  mp_impl->ENET0_GMII_TX_CLK(ENET0_GMII_TX_CLK);
982  mp_impl->ENET0_MDIO_I(ENET0_MDIO_I);
983  mp_impl->ENET0_EXT_INTIN(ENET0_EXT_INTIN);
984  mp_impl->ENET0_GMII_RXD(ENET0_GMII_RXD);
985  mp_impl->GPIO_I(GPIO_I);
986  mp_impl->GPIO_O(GPIO_O);
987  mp_impl->GPIO_T(GPIO_T);
988  mp_impl->TTC0_WAVE0_OUT(TTC0_WAVE0_OUT);
989  mp_impl->TTC0_WAVE1_OUT(TTC0_WAVE1_OUT);
990  mp_impl->TTC0_WAVE2_OUT(TTC0_WAVE2_OUT);
991  mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
992  mp_impl->S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT);
993  mp_impl->S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT);
994  mp_impl->S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT);
995  mp_impl->S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT);
996  mp_impl->S_AXI_HP0_ACLK(S_AXI_HP0_ACLK);
997  mp_impl->S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN);
998  mp_impl->S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN);
999  mp_impl->IRQ_F2P(IRQ_F2P);
1000  mp_impl->FCLK_CLK0(FCLK_CLK0);
1001  mp_impl->FCLK_CLK1(FCLK_CLK1);
1002  mp_impl->FCLK_CLK2(FCLK_CLK2);
1003  mp_impl->FCLK_CLK3(FCLK_CLK3);
1004  mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
1005  mp_impl->MIO(MIO);
1006  mp_impl->DDR_CAS_n(DDR_CAS_n);
1007  mp_impl->DDR_CKE(DDR_CKE);
1008  mp_impl->DDR_Clk_n(DDR_Clk_n);
1009  mp_impl->DDR_Clk(DDR_Clk);
1010  mp_impl->DDR_CS_n(DDR_CS_n);
1011  mp_impl->DDR_DRSTB(DDR_DRSTB);
1012  mp_impl->DDR_ODT(DDR_ODT);
1013  mp_impl->DDR_RAS_n(DDR_RAS_n);
1014  mp_impl->DDR_WEB(DDR_WEB);
1015  mp_impl->DDR_BankAddr(DDR_BankAddr);
1016  mp_impl->DDR_Addr(DDR_Addr);
1017  mp_impl->DDR_VRN(DDR_VRN);
1018  mp_impl->DDR_VRP(DDR_VRP);
1019  mp_impl->DDR_DM(DDR_DM);
1020  mp_impl->DDR_DQ(DDR_DQ);
1021  mp_impl->DDR_DQS_n(DDR_DQS_n);
1022  mp_impl->DDR_DQS(DDR_DQS);
1023  mp_impl->PS_SRSTB(PS_SRSTB);
1024  mp_impl->PS_CLK(PS_CLK);
1025  mp_impl->PS_PORB(PS_PORB);
1026 
1027  // initialize transactors
1028  mp_M_AXI_GP0_transactor = NULL;
1029  mp_M_AXI_GP0_ARLOCK_converter = NULL;
1030  mp_M_AXI_GP0_AWLOCK_converter = NULL;
1031  mp_M_AXI_GP0_ARLEN_converter = NULL;
1032  mp_M_AXI_GP0_AWLEN_converter = NULL;
1033  mp_S_AXI_HP0_transactor = NULL;
1034  mp_S_AXI_HP0_ARLOCK_converter = NULL;
1035  mp_S_AXI_HP0_AWLOCK_converter = NULL;
1036  mp_S_AXI_HP0_ARLEN_converter = NULL;
1037  mp_S_AXI_HP0_AWLEN_converter = NULL;
1038 
1039  // Instantiate Socket Stubs
1040 
1041  // configure M_AXI_GP0_transactor
1042  xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
1043  M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
1044  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
1045  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
1046  M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
1047  M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
1048  M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
1049  M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
1050  M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
1051  M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
1052  M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
1053  M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
1054  M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
1055  M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
1056  M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
1057  M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
1058  M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
1059  M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
1060  M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
1061  M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
1062  M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
1063  M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
1064  M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
1065  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
1066  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
1067  M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
1068  M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
1069  M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
1070  M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
1071  M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.000");
1072  M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
1073  M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
1074  M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
1075 
1076  mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
1077  mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
1078  mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
1079  mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
1080  mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
1081  mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
1082  mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
1083  mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
1084  mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
1085  mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
1086  mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
1087  mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
1088  mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
1089  mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
1090  mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
1091  mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
1092  mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
1093  mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
1094  mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
1095  mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
1096  mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
1097  mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
1098  mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
1099  mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
1100  mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
1101  mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
1102  mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
1103  mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
1104  mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
1105  mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
1106  mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
1107  mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
1108  mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
1109  mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
1110  mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
1111  mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
1112  mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
1113  mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
1114  mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
1115  mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
1116  mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
1117  mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
1118  mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
1119  mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
1120  mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
1121  mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
1122  mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
1123  mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
1124  mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
1125  mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
1126  mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
1127  m_M_AXI_GP0_transactor_rst_signal.write(1);
1128  mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
1129  // configure S_AXI_HP0_transactor
1130  xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
1131  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
1132  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
1133  S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "64");
1134  S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
1135  S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
1136  S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
1137  S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
1138  S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
1139  S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
1140  S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
1141  S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
1142  S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
1143  S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
1144  S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
1145  S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
1146  S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
1147  S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
1148  S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
1149  S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
1150  S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
1151  S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
1152  S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
1153  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
1154  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
1155  S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
1156  S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
1157  S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
1158  S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
1159  S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.000");
1160  S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
1161  S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
1162  S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
1163 
1164  mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
1165  mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
1166  mp_S_AXI_HP0_transactor->AWREADY(S_AXI_HP0_AWREADY);
1167  mp_S_AXI_HP0_transactor->BVALID(S_AXI_HP0_BVALID);
1168  mp_S_AXI_HP0_transactor->RLAST(S_AXI_HP0_RLAST);
1169  mp_S_AXI_HP0_transactor->RVALID(S_AXI_HP0_RVALID);
1170  mp_S_AXI_HP0_transactor->WREADY(S_AXI_HP0_WREADY);
1171  mp_S_AXI_HP0_transactor->BRESP(S_AXI_HP0_BRESP);
1172  mp_S_AXI_HP0_transactor->RRESP(S_AXI_HP0_RRESP);
1173  mp_S_AXI_HP0_transactor->BID(S_AXI_HP0_BID);
1174  mp_S_AXI_HP0_transactor->RID(S_AXI_HP0_RID);
1175  mp_S_AXI_HP0_transactor->RDATA(S_AXI_HP0_RDATA);
1176  mp_S_AXI_HP0_transactor->ARVALID(S_AXI_HP0_ARVALID);
1177  mp_S_AXI_HP0_transactor->AWVALID(S_AXI_HP0_AWVALID);
1178  mp_S_AXI_HP0_transactor->BREADY(S_AXI_HP0_BREADY);
1179  mp_S_AXI_HP0_transactor->RREADY(S_AXI_HP0_RREADY);
1180  mp_S_AXI_HP0_transactor->WLAST(S_AXI_HP0_WLAST);
1181  mp_S_AXI_HP0_transactor->WVALID(S_AXI_HP0_WVALID);
1182  mp_S_AXI_HP0_transactor->ARBURST(S_AXI_HP0_ARBURST);
1183  mp_S_AXI_HP0_ARLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_ARLOCK_converter");
1184  mp_S_AXI_HP0_ARLOCK_converter->vector_in(S_AXI_HP0_ARLOCK);
1185  mp_S_AXI_HP0_ARLOCK_converter->scalar_out(m_S_AXI_HP0_ARLOCK_converter_signal);
1186  mp_S_AXI_HP0_transactor->ARLOCK(m_S_AXI_HP0_ARLOCK_converter_signal);
1187  mp_S_AXI_HP0_transactor->ARSIZE(S_AXI_HP0_ARSIZE);
1188  mp_S_AXI_HP0_transactor->AWBURST(S_AXI_HP0_AWBURST);
1189  mp_S_AXI_HP0_AWLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_AWLOCK_converter");
1190  mp_S_AXI_HP0_AWLOCK_converter->vector_in(S_AXI_HP0_AWLOCK);
1191  mp_S_AXI_HP0_AWLOCK_converter->scalar_out(m_S_AXI_HP0_AWLOCK_converter_signal);
1192  mp_S_AXI_HP0_transactor->AWLOCK(m_S_AXI_HP0_AWLOCK_converter_signal);
1193  mp_S_AXI_HP0_transactor->AWSIZE(S_AXI_HP0_AWSIZE);
1194  mp_S_AXI_HP0_transactor->ARPROT(S_AXI_HP0_ARPROT);
1195  mp_S_AXI_HP0_transactor->AWPROT(S_AXI_HP0_AWPROT);
1196  mp_S_AXI_HP0_transactor->ARADDR(S_AXI_HP0_ARADDR);
1197  mp_S_AXI_HP0_transactor->AWADDR(S_AXI_HP0_AWADDR);
1198  mp_S_AXI_HP0_transactor->ARCACHE(S_AXI_HP0_ARCACHE);
1199  mp_S_AXI_HP0_ARLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_ARLEN_converter");
1200  mp_S_AXI_HP0_ARLEN_converter->vector_in(S_AXI_HP0_ARLEN);
1201  mp_S_AXI_HP0_ARLEN_converter->vector_out(m_S_AXI_HP0_ARLEN_converter_signal);
1202  mp_S_AXI_HP0_transactor->ARLEN(m_S_AXI_HP0_ARLEN_converter_signal);
1203  mp_S_AXI_HP0_transactor->ARQOS(S_AXI_HP0_ARQOS);
1204  mp_S_AXI_HP0_transactor->AWCACHE(S_AXI_HP0_AWCACHE);
1205  mp_S_AXI_HP0_AWLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_AWLEN_converter");
1206  mp_S_AXI_HP0_AWLEN_converter->vector_in(S_AXI_HP0_AWLEN);
1207  mp_S_AXI_HP0_AWLEN_converter->vector_out(m_S_AXI_HP0_AWLEN_converter_signal);
1208  mp_S_AXI_HP0_transactor->AWLEN(m_S_AXI_HP0_AWLEN_converter_signal);
1209  mp_S_AXI_HP0_transactor->AWQOS(S_AXI_HP0_AWQOS);
1210  mp_S_AXI_HP0_transactor->ARID(S_AXI_HP0_ARID);
1211  mp_S_AXI_HP0_transactor->AWID(S_AXI_HP0_AWID);
1212  mp_S_AXI_HP0_transactor->WDATA(S_AXI_HP0_WDATA);
1213  mp_S_AXI_HP0_transactor->WSTRB(S_AXI_HP0_WSTRB);
1214  mp_S_AXI_HP0_transactor->CLK(S_AXI_HP0_ACLK);
1215  m_S_AXI_HP0_transactor_rst_signal.write(1);
1216  mp_S_AXI_HP0_transactor->RST(m_S_AXI_HP0_transactor_rst_signal);
1217 
1218  // initialize transactors stubs
1219  M_AXI_GP0_transactor_initiator_wr_socket_stub = nullptr;
1220  M_AXI_GP0_transactor_initiator_rd_socket_stub = nullptr;
1221  S_AXI_HP0_transactor_target_wr_socket_stub = nullptr;
1222  S_AXI_HP0_transactor_target_rd_socket_stub = nullptr;
1223 
1224 }
1225 
1226 void design_1_processing_system7_0_0::before_end_of_elaboration()
1227 {
1228  // configure 'M_AXI_GP0' transactor
1229  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
1230  {
1231  mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
1232  mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
1233 
1234  }
1235  else
1236  {
1237  M_AXI_GP0_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
1238  M_AXI_GP0_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
1239  M_AXI_GP0_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
1240  M_AXI_GP0_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
1241  mp_M_AXI_GP0_transactor->disable_transactor();
1242  }
1243 
1244  // configure 'S_AXI_HP0' transactor
1245  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
1246  {
1247  mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
1248  mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
1249 
1250  }
1251  else
1252  {
1253  S_AXI_HP0_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
1254  S_AXI_HP0_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
1255  S_AXI_HP0_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
1256  S_AXI_HP0_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
1257  mp_S_AXI_HP0_transactor->disable_transactor();
1258  }
1259 
1260 }
1261 
1262 #endif // VCSSYSTEMC
1263 
1264 
1265 
1266 
1267 #ifdef MTI_SYSTEMC
1268 design_1_processing_system7_0_0::design_1_processing_system7_0_0(const sc_core::sc_module_name& nm) : design_1_processing_system7_0_0_sc(nm), ENET0_GMII_TX_EN("ENET0_GMII_TX_EN"), ENET0_GMII_TX_ER("ENET0_GMII_TX_ER"), ENET0_MDIO_MDC("ENET0_MDIO_MDC"), ENET0_MDIO_O("ENET0_MDIO_O"), ENET0_MDIO_T("ENET0_MDIO_T"), ENET0_GMII_TXD("ENET0_GMII_TXD"), ENET0_GMII_COL("ENET0_GMII_COL"), ENET0_GMII_CRS("ENET0_GMII_CRS"), ENET0_GMII_RX_CLK("ENET0_GMII_RX_CLK"), ENET0_GMII_RX_DV("ENET0_GMII_RX_DV"), ENET0_GMII_RX_ER("ENET0_GMII_RX_ER"), ENET0_GMII_TX_CLK("ENET0_GMII_TX_CLK"), ENET0_MDIO_I("ENET0_MDIO_I"), ENET0_EXT_INTIN("ENET0_EXT_INTIN"), ENET0_GMII_RXD("ENET0_GMII_RXD"), GPIO_I("GPIO_I"), GPIO_O("GPIO_O"), GPIO_T("GPIO_T"), TTC0_WAVE0_OUT("TTC0_WAVE0_OUT"), TTC0_WAVE1_OUT("TTC0_WAVE1_OUT"), TTC0_WAVE2_OUT("TTC0_WAVE2_OUT"), M_AXI_GP0_ARVALID("M_AXI_GP0_ARVALID"), M_AXI_GP0_AWVALID("M_AXI_GP0_AWVALID"), M_AXI_GP0_BREADY("M_AXI_GP0_BREADY"), M_AXI_GP0_RREADY("M_AXI_GP0_RREADY"), M_AXI_GP0_WLAST("M_AXI_GP0_WLAST"), M_AXI_GP0_WVALID("M_AXI_GP0_WVALID"), M_AXI_GP0_ARID("M_AXI_GP0_ARID"), M_AXI_GP0_AWID("M_AXI_GP0_AWID"), M_AXI_GP0_WID("M_AXI_GP0_WID"), M_AXI_GP0_ARBURST("M_AXI_GP0_ARBURST"), M_AXI_GP0_ARLOCK("M_AXI_GP0_ARLOCK"), M_AXI_GP0_ARSIZE("M_AXI_GP0_ARSIZE"), M_AXI_GP0_AWBURST("M_AXI_GP0_AWBURST"), M_AXI_GP0_AWLOCK("M_AXI_GP0_AWLOCK"), M_AXI_GP0_AWSIZE("M_AXI_GP0_AWSIZE"), M_AXI_GP0_ARPROT("M_AXI_GP0_ARPROT"), M_AXI_GP0_AWPROT("M_AXI_GP0_AWPROT"), M_AXI_GP0_ARADDR("M_AXI_GP0_ARADDR"), M_AXI_GP0_AWADDR("M_AXI_GP0_AWADDR"), M_AXI_GP0_WDATA("M_AXI_GP0_WDATA"), M_AXI_GP0_ARCACHE("M_AXI_GP0_ARCACHE"), M_AXI_GP0_ARLEN("M_AXI_GP0_ARLEN"), M_AXI_GP0_ARQOS("M_AXI_GP0_ARQOS"), M_AXI_GP0_AWCACHE("M_AXI_GP0_AWCACHE"), M_AXI_GP0_AWLEN("M_AXI_GP0_AWLEN"), M_AXI_GP0_AWQOS("M_AXI_GP0_AWQOS"), M_AXI_GP0_WSTRB("M_AXI_GP0_WSTRB"), M_AXI_GP0_ACLK("M_AXI_GP0_ACLK"), M_AXI_GP0_ARREADY("M_AXI_GP0_ARREADY"), M_AXI_GP0_AWREADY("M_AXI_GP0_AWREADY"), M_AXI_GP0_BVALID("M_AXI_GP0_BVALID"), M_AXI_GP0_RLAST("M_AXI_GP0_RLAST"), M_AXI_GP0_RVALID("M_AXI_GP0_RVALID"), M_AXI_GP0_WREADY("M_AXI_GP0_WREADY"), M_AXI_GP0_BID("M_AXI_GP0_BID"), M_AXI_GP0_RID("M_AXI_GP0_RID"), M_AXI_GP0_BRESP("M_AXI_GP0_BRESP"), M_AXI_GP0_RRESP("M_AXI_GP0_RRESP"), M_AXI_GP0_RDATA("M_AXI_GP0_RDATA"), S_AXI_HP0_ARREADY("S_AXI_HP0_ARREADY"), S_AXI_HP0_AWREADY("S_AXI_HP0_AWREADY"), S_AXI_HP0_BVALID("S_AXI_HP0_BVALID"), S_AXI_HP0_RLAST("S_AXI_HP0_RLAST"), S_AXI_HP0_RVALID("S_AXI_HP0_RVALID"), S_AXI_HP0_WREADY("S_AXI_HP0_WREADY"), S_AXI_HP0_BRESP("S_AXI_HP0_BRESP"), S_AXI_HP0_RRESP("S_AXI_HP0_RRESP"), S_AXI_HP0_BID("S_AXI_HP0_BID"), S_AXI_HP0_RID("S_AXI_HP0_RID"), S_AXI_HP0_RDATA("S_AXI_HP0_RDATA"), S_AXI_HP0_RCOUNT("S_AXI_HP0_RCOUNT"), S_AXI_HP0_WCOUNT("S_AXI_HP0_WCOUNT"), S_AXI_HP0_RACOUNT("S_AXI_HP0_RACOUNT"), S_AXI_HP0_WACOUNT("S_AXI_HP0_WACOUNT"), S_AXI_HP0_ACLK("S_AXI_HP0_ACLK"), S_AXI_HP0_ARVALID("S_AXI_HP0_ARVALID"), S_AXI_HP0_AWVALID("S_AXI_HP0_AWVALID"), S_AXI_HP0_BREADY("S_AXI_HP0_BREADY"), S_AXI_HP0_RDISSUECAP1_EN("S_AXI_HP0_RDISSUECAP1_EN"), S_AXI_HP0_RREADY("S_AXI_HP0_RREADY"), S_AXI_HP0_WLAST("S_AXI_HP0_WLAST"), S_AXI_HP0_WRISSUECAP1_EN("S_AXI_HP0_WRISSUECAP1_EN"), S_AXI_HP0_WVALID("S_AXI_HP0_WVALID"), S_AXI_HP0_ARBURST("S_AXI_HP0_ARBURST"), S_AXI_HP0_ARLOCK("S_AXI_HP0_ARLOCK"), S_AXI_HP0_ARSIZE("S_AXI_HP0_ARSIZE"), S_AXI_HP0_AWBURST("S_AXI_HP0_AWBURST"), S_AXI_HP0_AWLOCK("S_AXI_HP0_AWLOCK"), S_AXI_HP0_AWSIZE("S_AXI_HP0_AWSIZE"), S_AXI_HP0_ARPROT("S_AXI_HP0_ARPROT"), S_AXI_HP0_AWPROT("S_AXI_HP0_AWPROT"), S_AXI_HP0_ARADDR("S_AXI_HP0_ARADDR"), S_AXI_HP0_AWADDR("S_AXI_HP0_AWADDR"), S_AXI_HP0_ARCACHE("S_AXI_HP0_ARCACHE"), S_AXI_HP0_ARLEN("S_AXI_HP0_ARLEN"), S_AXI_HP0_ARQOS("S_AXI_HP0_ARQOS"), S_AXI_HP0_AWCACHE("S_AXI_HP0_AWCACHE"), S_AXI_HP0_AWLEN("S_AXI_HP0_AWLEN"), S_AXI_HP0_AWQOS("S_AXI_HP0_AWQOS"), S_AXI_HP0_ARID("S_AXI_HP0_ARID"), S_AXI_HP0_AWID("S_AXI_HP0_AWID"), S_AXI_HP0_WID("S_AXI_HP0_WID"), S_AXI_HP0_WDATA("S_AXI_HP0_WDATA"), S_AXI_HP0_WSTRB("S_AXI_HP0_WSTRB"), IRQ_F2P("IRQ_F2P"), FCLK_CLK0("FCLK_CLK0"), FCLK_CLK1("FCLK_CLK1"), FCLK_CLK2("FCLK_CLK2"), FCLK_CLK3("FCLK_CLK3"), FCLK_RESET0_N("FCLK_RESET0_N"), MIO("MIO"), DDR_CAS_n("DDR_CAS_n"), DDR_CKE("DDR_CKE"), DDR_Clk_n("DDR_Clk_n"), DDR_Clk("DDR_Clk"), DDR_CS_n("DDR_CS_n"), DDR_DRSTB("DDR_DRSTB"), DDR_ODT("DDR_ODT"), DDR_RAS_n("DDR_RAS_n"), DDR_WEB("DDR_WEB"), DDR_BankAddr("DDR_BankAddr"), DDR_Addr("DDR_Addr"), DDR_VRN("DDR_VRN"), DDR_VRP("DDR_VRP"), DDR_DM("DDR_DM"), DDR_DQ("DDR_DQ"), DDR_DQS_n("DDR_DQS_n"), DDR_DQS("DDR_DQS"), PS_SRSTB("PS_SRSTB"), PS_CLK("PS_CLK"), PS_PORB("PS_PORB")
1269 {
1270  // initialize pins
1271  mp_impl->ENET0_GMII_TX_EN(ENET0_GMII_TX_EN);
1272  mp_impl->ENET0_GMII_TX_ER(ENET0_GMII_TX_ER);
1273  mp_impl->ENET0_MDIO_MDC(ENET0_MDIO_MDC);
1274  mp_impl->ENET0_MDIO_O(ENET0_MDIO_O);
1275  mp_impl->ENET0_MDIO_T(ENET0_MDIO_T);
1276  mp_impl->ENET0_GMII_TXD(ENET0_GMII_TXD);
1277  mp_impl->ENET0_GMII_COL(ENET0_GMII_COL);
1278  mp_impl->ENET0_GMII_CRS(ENET0_GMII_CRS);
1279  mp_impl->ENET0_GMII_RX_CLK(ENET0_GMII_RX_CLK);
1280  mp_impl->ENET0_GMII_RX_DV(ENET0_GMII_RX_DV);
1281  mp_impl->ENET0_GMII_RX_ER(ENET0_GMII_RX_ER);
1282  mp_impl->ENET0_GMII_TX_CLK(ENET0_GMII_TX_CLK);
1283  mp_impl->ENET0_MDIO_I(ENET0_MDIO_I);
1284  mp_impl->ENET0_EXT_INTIN(ENET0_EXT_INTIN);
1285  mp_impl->ENET0_GMII_RXD(ENET0_GMII_RXD);
1286  mp_impl->GPIO_I(GPIO_I);
1287  mp_impl->GPIO_O(GPIO_O);
1288  mp_impl->GPIO_T(GPIO_T);
1289  mp_impl->TTC0_WAVE0_OUT(TTC0_WAVE0_OUT);
1290  mp_impl->TTC0_WAVE1_OUT(TTC0_WAVE1_OUT);
1291  mp_impl->TTC0_WAVE2_OUT(TTC0_WAVE2_OUT);
1292  mp_impl->M_AXI_GP0_ACLK(M_AXI_GP0_ACLK);
1293  mp_impl->S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT);
1294  mp_impl->S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT);
1295  mp_impl->S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT);
1296  mp_impl->S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT);
1297  mp_impl->S_AXI_HP0_ACLK(S_AXI_HP0_ACLK);
1298  mp_impl->S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN);
1299  mp_impl->S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN);
1300  mp_impl->IRQ_F2P(IRQ_F2P);
1301  mp_impl->FCLK_CLK0(FCLK_CLK0);
1302  mp_impl->FCLK_CLK1(FCLK_CLK1);
1303  mp_impl->FCLK_CLK2(FCLK_CLK2);
1304  mp_impl->FCLK_CLK3(FCLK_CLK3);
1305  mp_impl->FCLK_RESET0_N(FCLK_RESET0_N);
1306  mp_impl->MIO(MIO);
1307  mp_impl->DDR_CAS_n(DDR_CAS_n);
1308  mp_impl->DDR_CKE(DDR_CKE);
1309  mp_impl->DDR_Clk_n(DDR_Clk_n);
1310  mp_impl->DDR_Clk(DDR_Clk);
1311  mp_impl->DDR_CS_n(DDR_CS_n);
1312  mp_impl->DDR_DRSTB(DDR_DRSTB);
1313  mp_impl->DDR_ODT(DDR_ODT);
1314  mp_impl->DDR_RAS_n(DDR_RAS_n);
1315  mp_impl->DDR_WEB(DDR_WEB);
1316  mp_impl->DDR_BankAddr(DDR_BankAddr);
1317  mp_impl->DDR_Addr(DDR_Addr);
1318  mp_impl->DDR_VRN(DDR_VRN);
1319  mp_impl->DDR_VRP(DDR_VRP);
1320  mp_impl->DDR_DM(DDR_DM);
1321  mp_impl->DDR_DQ(DDR_DQ);
1322  mp_impl->DDR_DQS_n(DDR_DQS_n);
1323  mp_impl->DDR_DQS(DDR_DQS);
1324  mp_impl->PS_SRSTB(PS_SRSTB);
1325  mp_impl->PS_CLK(PS_CLK);
1326  mp_impl->PS_PORB(PS_PORB);
1327 
1328  // initialize transactors
1329  mp_M_AXI_GP0_transactor = NULL;
1330  mp_M_AXI_GP0_ARLOCK_converter = NULL;
1331  mp_M_AXI_GP0_AWLOCK_converter = NULL;
1332  mp_M_AXI_GP0_ARLEN_converter = NULL;
1333  mp_M_AXI_GP0_AWLEN_converter = NULL;
1334  mp_S_AXI_HP0_transactor = NULL;
1335  mp_S_AXI_HP0_ARLOCK_converter = NULL;
1336  mp_S_AXI_HP0_AWLOCK_converter = NULL;
1337  mp_S_AXI_HP0_ARLEN_converter = NULL;
1338  mp_S_AXI_HP0_AWLEN_converter = NULL;
1339 
1340  // Instantiate Socket Stubs
1341 
1342  // configure M_AXI_GP0_transactor
1343  xsc::common_cpp::properties M_AXI_GP0_transactor_param_props;
1344  M_AXI_GP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
1345  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
1346  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
1347  M_AXI_GP0_transactor_param_props.addLong("DATA_WIDTH", "32");
1348  M_AXI_GP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
1349  M_AXI_GP0_transactor_param_props.addLong("ID_WIDTH", "12");
1350  M_AXI_GP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
1351  M_AXI_GP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
1352  M_AXI_GP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
1353  M_AXI_GP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
1354  M_AXI_GP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
1355  M_AXI_GP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
1356  M_AXI_GP0_transactor_param_props.addLong("HAS_BURST", "1");
1357  M_AXI_GP0_transactor_param_props.addLong("HAS_LOCK", "1");
1358  M_AXI_GP0_transactor_param_props.addLong("HAS_PROT", "1");
1359  M_AXI_GP0_transactor_param_props.addLong("HAS_CACHE", "1");
1360  M_AXI_GP0_transactor_param_props.addLong("HAS_QOS", "1");
1361  M_AXI_GP0_transactor_param_props.addLong("HAS_REGION", "0");
1362  M_AXI_GP0_transactor_param_props.addLong("HAS_WSTRB", "1");
1363  M_AXI_GP0_transactor_param_props.addLong("HAS_BRESP", "1");
1364  M_AXI_GP0_transactor_param_props.addLong("HAS_RRESP", "1");
1365  M_AXI_GP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
1366  M_AXI_GP0_transactor_param_props.addLong("NUM_READ_THREADS", "4");
1367  M_AXI_GP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
1368  M_AXI_GP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
1369  M_AXI_GP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
1370  M_AXI_GP0_transactor_param_props.addLong("HAS_SIZE", "1");
1371  M_AXI_GP0_transactor_param_props.addLong("HAS_RESET", "0");
1372  M_AXI_GP0_transactor_param_props.addFloat("PHASE", "0.000");
1373  M_AXI_GP0_transactor_param_props.addString("PROTOCOL", "AXI3");
1374  M_AXI_GP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
1375  M_AXI_GP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
1376 
1377  mp_M_AXI_GP0_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_GP0_transactor", M_AXI_GP0_transactor_param_props);
1378  mp_M_AXI_GP0_transactor->ARVALID(M_AXI_GP0_ARVALID);
1379  mp_M_AXI_GP0_transactor->AWVALID(M_AXI_GP0_AWVALID);
1380  mp_M_AXI_GP0_transactor->BREADY(M_AXI_GP0_BREADY);
1381  mp_M_AXI_GP0_transactor->RREADY(M_AXI_GP0_RREADY);
1382  mp_M_AXI_GP0_transactor->WLAST(M_AXI_GP0_WLAST);
1383  mp_M_AXI_GP0_transactor->WVALID(M_AXI_GP0_WVALID);
1384  mp_M_AXI_GP0_transactor->ARID(M_AXI_GP0_ARID);
1385  mp_M_AXI_GP0_transactor->AWID(M_AXI_GP0_AWID);
1386  mp_M_AXI_GP0_transactor->ARBURST(M_AXI_GP0_ARBURST);
1387  mp_M_AXI_GP0_ARLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_ARLOCK_converter");
1388  mp_M_AXI_GP0_ARLOCK_converter->scalar_in(m_M_AXI_GP0_ARLOCK_converter_signal);
1389  mp_M_AXI_GP0_ARLOCK_converter->vector_out(M_AXI_GP0_ARLOCK);
1390  mp_M_AXI_GP0_transactor->ARLOCK(m_M_AXI_GP0_ARLOCK_converter_signal);
1391  mp_M_AXI_GP0_transactor->ARSIZE(M_AXI_GP0_ARSIZE);
1392  mp_M_AXI_GP0_transactor->AWBURST(M_AXI_GP0_AWBURST);
1393  mp_M_AXI_GP0_AWLOCK_converter = new xsc::common::scalar2vectorN_converter<2>("M_AXI_GP0_AWLOCK_converter");
1394  mp_M_AXI_GP0_AWLOCK_converter->scalar_in(m_M_AXI_GP0_AWLOCK_converter_signal);
1395  mp_M_AXI_GP0_AWLOCK_converter->vector_out(M_AXI_GP0_AWLOCK);
1396  mp_M_AXI_GP0_transactor->AWLOCK(m_M_AXI_GP0_AWLOCK_converter_signal);
1397  mp_M_AXI_GP0_transactor->AWSIZE(M_AXI_GP0_AWSIZE);
1398  mp_M_AXI_GP0_transactor->ARPROT(M_AXI_GP0_ARPROT);
1399  mp_M_AXI_GP0_transactor->AWPROT(M_AXI_GP0_AWPROT);
1400  mp_M_AXI_GP0_transactor->ARADDR(M_AXI_GP0_ARADDR);
1401  mp_M_AXI_GP0_transactor->AWADDR(M_AXI_GP0_AWADDR);
1402  mp_M_AXI_GP0_transactor->WDATA(M_AXI_GP0_WDATA);
1403  mp_M_AXI_GP0_transactor->ARCACHE(M_AXI_GP0_ARCACHE);
1404  mp_M_AXI_GP0_ARLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_ARLEN_converter");
1405  mp_M_AXI_GP0_ARLEN_converter->vector_in(m_M_AXI_GP0_ARLEN_converter_signal);
1406  mp_M_AXI_GP0_ARLEN_converter->vector_out(M_AXI_GP0_ARLEN);
1407  mp_M_AXI_GP0_transactor->ARLEN(m_M_AXI_GP0_ARLEN_converter_signal);
1408  mp_M_AXI_GP0_transactor->ARQOS(M_AXI_GP0_ARQOS);
1409  mp_M_AXI_GP0_transactor->AWCACHE(M_AXI_GP0_AWCACHE);
1410  mp_M_AXI_GP0_AWLEN_converter = new xsc::common::vector2vector_converter<8,4>("M_AXI_GP0_AWLEN_converter");
1411  mp_M_AXI_GP0_AWLEN_converter->vector_in(m_M_AXI_GP0_AWLEN_converter_signal);
1412  mp_M_AXI_GP0_AWLEN_converter->vector_out(M_AXI_GP0_AWLEN);
1413  mp_M_AXI_GP0_transactor->AWLEN(m_M_AXI_GP0_AWLEN_converter_signal);
1414  mp_M_AXI_GP0_transactor->AWQOS(M_AXI_GP0_AWQOS);
1415  mp_M_AXI_GP0_transactor->WSTRB(M_AXI_GP0_WSTRB);
1416  mp_M_AXI_GP0_transactor->ARREADY(M_AXI_GP0_ARREADY);
1417  mp_M_AXI_GP0_transactor->AWREADY(M_AXI_GP0_AWREADY);
1418  mp_M_AXI_GP0_transactor->BVALID(M_AXI_GP0_BVALID);
1419  mp_M_AXI_GP0_transactor->RLAST(M_AXI_GP0_RLAST);
1420  mp_M_AXI_GP0_transactor->RVALID(M_AXI_GP0_RVALID);
1421  mp_M_AXI_GP0_transactor->WREADY(M_AXI_GP0_WREADY);
1422  mp_M_AXI_GP0_transactor->BID(M_AXI_GP0_BID);
1423  mp_M_AXI_GP0_transactor->RID(M_AXI_GP0_RID);
1424  mp_M_AXI_GP0_transactor->BRESP(M_AXI_GP0_BRESP);
1425  mp_M_AXI_GP0_transactor->RRESP(M_AXI_GP0_RRESP);
1426  mp_M_AXI_GP0_transactor->RDATA(M_AXI_GP0_RDATA);
1427  mp_M_AXI_GP0_transactor->CLK(M_AXI_GP0_ACLK);
1428  m_M_AXI_GP0_transactor_rst_signal.write(1);
1429  mp_M_AXI_GP0_transactor->RST(m_M_AXI_GP0_transactor_rst_signal);
1430  // configure S_AXI_HP0_transactor
1431  xsc::common_cpp::properties S_AXI_HP0_transactor_param_props;
1432  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
1433  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
1434  S_AXI_HP0_transactor_param_props.addLong("DATA_WIDTH", "64");
1435  S_AXI_HP0_transactor_param_props.addLong("FREQ_HZ", "125000000");
1436  S_AXI_HP0_transactor_param_props.addLong("ID_WIDTH", "6");
1437  S_AXI_HP0_transactor_param_props.addLong("ADDR_WIDTH", "32");
1438  S_AXI_HP0_transactor_param_props.addLong("AWUSER_WIDTH", "0");
1439  S_AXI_HP0_transactor_param_props.addLong("ARUSER_WIDTH", "0");
1440  S_AXI_HP0_transactor_param_props.addLong("WUSER_WIDTH", "0");
1441  S_AXI_HP0_transactor_param_props.addLong("RUSER_WIDTH", "0");
1442  S_AXI_HP0_transactor_param_props.addLong("BUSER_WIDTH", "0");
1443  S_AXI_HP0_transactor_param_props.addLong("HAS_BURST", "1");
1444  S_AXI_HP0_transactor_param_props.addLong("HAS_LOCK", "1");
1445  S_AXI_HP0_transactor_param_props.addLong("HAS_PROT", "1");
1446  S_AXI_HP0_transactor_param_props.addLong("HAS_CACHE", "1");
1447  S_AXI_HP0_transactor_param_props.addLong("HAS_QOS", "1");
1448  S_AXI_HP0_transactor_param_props.addLong("HAS_REGION", "0");
1449  S_AXI_HP0_transactor_param_props.addLong("HAS_WSTRB", "1");
1450  S_AXI_HP0_transactor_param_props.addLong("HAS_BRESP", "1");
1451  S_AXI_HP0_transactor_param_props.addLong("HAS_RRESP", "1");
1452  S_AXI_HP0_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
1453  S_AXI_HP0_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
1454  S_AXI_HP0_transactor_param_props.addLong("NUM_READ_THREADS", "1");
1455  S_AXI_HP0_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
1456  S_AXI_HP0_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
1457  S_AXI_HP0_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
1458  S_AXI_HP0_transactor_param_props.addLong("HAS_SIZE", "1");
1459  S_AXI_HP0_transactor_param_props.addLong("HAS_RESET", "0");
1460  S_AXI_HP0_transactor_param_props.addFloat("PHASE", "0.000");
1461  S_AXI_HP0_transactor_param_props.addString("PROTOCOL", "AXI3");
1462  S_AXI_HP0_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
1463  S_AXI_HP0_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
1464 
1465  mp_S_AXI_HP0_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,6,1,1,1,1,1>("S_AXI_HP0_transactor", S_AXI_HP0_transactor_param_props);
1466  mp_S_AXI_HP0_transactor->ARREADY(S_AXI_HP0_ARREADY);
1467  mp_S_AXI_HP0_transactor->AWREADY(S_AXI_HP0_AWREADY);
1468  mp_S_AXI_HP0_transactor->BVALID(S_AXI_HP0_BVALID);
1469  mp_S_AXI_HP0_transactor->RLAST(S_AXI_HP0_RLAST);
1470  mp_S_AXI_HP0_transactor->RVALID(S_AXI_HP0_RVALID);
1471  mp_S_AXI_HP0_transactor->WREADY(S_AXI_HP0_WREADY);
1472  mp_S_AXI_HP0_transactor->BRESP(S_AXI_HP0_BRESP);
1473  mp_S_AXI_HP0_transactor->RRESP(S_AXI_HP0_RRESP);
1474  mp_S_AXI_HP0_transactor->BID(S_AXI_HP0_BID);
1475  mp_S_AXI_HP0_transactor->RID(S_AXI_HP0_RID);
1476  mp_S_AXI_HP0_transactor->RDATA(S_AXI_HP0_RDATA);
1477  mp_S_AXI_HP0_transactor->ARVALID(S_AXI_HP0_ARVALID);
1478  mp_S_AXI_HP0_transactor->AWVALID(S_AXI_HP0_AWVALID);
1479  mp_S_AXI_HP0_transactor->BREADY(S_AXI_HP0_BREADY);
1480  mp_S_AXI_HP0_transactor->RREADY(S_AXI_HP0_RREADY);
1481  mp_S_AXI_HP0_transactor->WLAST(S_AXI_HP0_WLAST);
1482  mp_S_AXI_HP0_transactor->WVALID(S_AXI_HP0_WVALID);
1483  mp_S_AXI_HP0_transactor->ARBURST(S_AXI_HP0_ARBURST);
1484  mp_S_AXI_HP0_ARLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_ARLOCK_converter");
1485  mp_S_AXI_HP0_ARLOCK_converter->vector_in(S_AXI_HP0_ARLOCK);
1486  mp_S_AXI_HP0_ARLOCK_converter->scalar_out(m_S_AXI_HP0_ARLOCK_converter_signal);
1487  mp_S_AXI_HP0_transactor->ARLOCK(m_S_AXI_HP0_ARLOCK_converter_signal);
1488  mp_S_AXI_HP0_transactor->ARSIZE(S_AXI_HP0_ARSIZE);
1489  mp_S_AXI_HP0_transactor->AWBURST(S_AXI_HP0_AWBURST);
1490  mp_S_AXI_HP0_AWLOCK_converter = new xsc::common::vectorN2scalar_converter<2>("S_AXI_HP0_AWLOCK_converter");
1491  mp_S_AXI_HP0_AWLOCK_converter->vector_in(S_AXI_HP0_AWLOCK);
1492  mp_S_AXI_HP0_AWLOCK_converter->scalar_out(m_S_AXI_HP0_AWLOCK_converter_signal);
1493  mp_S_AXI_HP0_transactor->AWLOCK(m_S_AXI_HP0_AWLOCK_converter_signal);
1494  mp_S_AXI_HP0_transactor->AWSIZE(S_AXI_HP0_AWSIZE);
1495  mp_S_AXI_HP0_transactor->ARPROT(S_AXI_HP0_ARPROT);
1496  mp_S_AXI_HP0_transactor->AWPROT(S_AXI_HP0_AWPROT);
1497  mp_S_AXI_HP0_transactor->ARADDR(S_AXI_HP0_ARADDR);
1498  mp_S_AXI_HP0_transactor->AWADDR(S_AXI_HP0_AWADDR);
1499  mp_S_AXI_HP0_transactor->ARCACHE(S_AXI_HP0_ARCACHE);
1500  mp_S_AXI_HP0_ARLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_ARLEN_converter");
1501  mp_S_AXI_HP0_ARLEN_converter->vector_in(S_AXI_HP0_ARLEN);
1502  mp_S_AXI_HP0_ARLEN_converter->vector_out(m_S_AXI_HP0_ARLEN_converter_signal);
1503  mp_S_AXI_HP0_transactor->ARLEN(m_S_AXI_HP0_ARLEN_converter_signal);
1504  mp_S_AXI_HP0_transactor->ARQOS(S_AXI_HP0_ARQOS);
1505  mp_S_AXI_HP0_transactor->AWCACHE(S_AXI_HP0_AWCACHE);
1506  mp_S_AXI_HP0_AWLEN_converter = new xsc::common::vector2vector_converter<4,8>("S_AXI_HP0_AWLEN_converter");
1507  mp_S_AXI_HP0_AWLEN_converter->vector_in(S_AXI_HP0_AWLEN);
1508  mp_S_AXI_HP0_AWLEN_converter->vector_out(m_S_AXI_HP0_AWLEN_converter_signal);
1509  mp_S_AXI_HP0_transactor->AWLEN(m_S_AXI_HP0_AWLEN_converter_signal);
1510  mp_S_AXI_HP0_transactor->AWQOS(S_AXI_HP0_AWQOS);
1511  mp_S_AXI_HP0_transactor->ARID(S_AXI_HP0_ARID);
1512  mp_S_AXI_HP0_transactor->AWID(S_AXI_HP0_AWID);
1513  mp_S_AXI_HP0_transactor->WDATA(S_AXI_HP0_WDATA);
1514  mp_S_AXI_HP0_transactor->WSTRB(S_AXI_HP0_WSTRB);
1515  mp_S_AXI_HP0_transactor->CLK(S_AXI_HP0_ACLK);
1516  m_S_AXI_HP0_transactor_rst_signal.write(1);
1517  mp_S_AXI_HP0_transactor->RST(m_S_AXI_HP0_transactor_rst_signal);
1518 
1519  // initialize transactors stubs
1520  M_AXI_GP0_transactor_initiator_wr_socket_stub = nullptr;
1521  M_AXI_GP0_transactor_initiator_rd_socket_stub = nullptr;
1522  S_AXI_HP0_transactor_target_wr_socket_stub = nullptr;
1523  S_AXI_HP0_transactor_target_rd_socket_stub = nullptr;
1524 
1525 }
1526 
1527 void design_1_processing_system7_0_0::before_end_of_elaboration()
1528 {
1529  // configure 'M_AXI_GP0' transactor
1530  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "M_AXI_GP0_TLM_MODE") != 1)
1531  {
1532  mp_impl->M_AXI_GP0_rd_socket->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
1533  mp_impl->M_AXI_GP0_wr_socket->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
1534 
1535  }
1536  else
1537  {
1538  M_AXI_GP0_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
1539  M_AXI_GP0_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_GP0_transactor->wr_socket));
1540  M_AXI_GP0_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
1541  M_AXI_GP0_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_GP0_transactor->rd_socket));
1542  mp_M_AXI_GP0_transactor->disable_transactor();
1543  }
1544 
1545  // configure 'S_AXI_HP0' transactor
1546  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_processing_system7_0_0", "S_AXI_HP0_TLM_MODE") != 1)
1547  {
1548  mp_impl->S_AXI_HP0_rd_socket->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
1549  mp_impl->S_AXI_HP0_wr_socket->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
1550 
1551  }
1552  else
1553  {
1554  S_AXI_HP0_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
1555  S_AXI_HP0_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_HP0_transactor->wr_socket));
1556  S_AXI_HP0_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
1557  S_AXI_HP0_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_HP0_transactor->rd_socket));
1558  mp_S_AXI_HP0_transactor->disable_transactor();
1559  }
1560 
1561 }
1562 
1563 #endif // MTI_SYSTEMC
1564 
1565 
1566 
1567 
1568 design_1_processing_system7_0_0::~design_1_processing_system7_0_0()
1569 {
1570  delete mp_M_AXI_GP0_transactor;
1571  delete mp_M_AXI_GP0_ARLOCK_converter;
1572  delete mp_M_AXI_GP0_AWLOCK_converter;
1573  delete mp_M_AXI_GP0_ARLEN_converter;
1574  delete mp_M_AXI_GP0_AWLEN_converter;
1575 
1576  delete mp_S_AXI_HP0_transactor;
1577  delete mp_S_AXI_HP0_ARLOCK_converter;
1578  delete mp_S_AXI_HP0_AWLOCK_converter;
1579  delete mp_S_AXI_HP0_ARLEN_converter;
1580  delete mp_S_AXI_HP0_AWLEN_converter;
1581 
1582 }
1583 
1584 #ifdef MTI_SYSTEMC
1585 SC_MODULE_EXPORT(design_1_processing_system7_0_0);
1586 #endif
1587 
1588 #ifdef XM_SYSTEMC
1589 XMSC_MODULE_EXPORT(design_1_processing_system7_0_0);
1590 #endif
1591 
1592 #ifdef RIVIERA
1593 SC_MODULE_EXPORT(design_1_processing_system7_0_0);
1594 SC_REGISTER_BV(64);
1595 #endif
1596 
M_AXI_GP0_ARID
bit< 11 :0 > M_AXI_GP0_ARID
Definition: design_1_processing_system7_0_0.sv:179
DDR_DQS_n
bit< 3 :0 > DDR_DQS_n
Definition: design_1_processing_system7_0_0.sv:672
M_AXI_GP0_RVALID
bit M_AXI_GP0_RVALID
Definition: design_1_processing_system7_0_0.sv:205
M_AXI_GP0_WSTRB
bit< 3 :0 > M_AXI_GP0_WSTRB
Definition: design_1_processing_system7_0_0.sv:199
S_AXI_HP0_AWLEN
bit< 3 :0 > S_AXI_HP0_AWLEN
Definition: design_1_processing_system7_0_0.sv:408
S_AXI_HP0_ARLEN
bit< 3 :0 > S_AXI_HP0_ARLEN
Definition: design_1_processing_system7_0_0.sv:405
S_AXI_HP0_ARPROT
bit< 2 :0 > S_AXI_HP0_ARPROT
Definition: design_1_processing_system7_0_0.sv:400
S_AXI_HP0_BID
bit< 5 :0 > S_AXI_HP0_BID
Definition: design_1_processing_system7_0_0.sv:378
S_AXI_HP0_AWLOCK
bit< 1 :0 > S_AXI_HP0_AWLOCK
Definition: design_1_processing_system7_0_0.sv:398
DDR_VRP
bit DDR_VRP
Definition: design_1_processing_system7_0_0.sv:669
design_1_auto_pc_1_sc::mp_impl
axi_protocol_converter * mp_impl
Definition: design_1_auto_pc_1_sc.h:89
M_AXI_GP0_AWVALID
bit M_AXI_GP0_AWVALID
Definition: design_1_processing_system7_0_0.sv:174
DDR_RAS_n
bit DDR_RAS_n
Definition: design_1_processing_system7_0_0.sv:664
S_AXI_HP0_ARVALID
bit S_AXI_HP0_ARVALID
Definition: design_1_processing_system7_0_0.sv:386
design_1_processing_system7_0_0_sc.h
M_AXI_GP0_AWQOS
bit< 3 :0 > M_AXI_GP0_AWQOS
Definition: design_1_processing_system7_0_0.sv:198
ENET0_MDIO_T
bit ENET0_MDIO_T
Definition: design_1_processing_system7_0_0.sv:13
DDR_CAS_n
bit DDR_CAS_n
Definition: design_1_processing_system7_0_0.sv:657
S_AXI_HP0_WVALID
bit S_AXI_HP0_WVALID
Definition: design_1_processing_system7_0_0.sv:393
S_AXI_HP0_RRESP
bit< 1 :0 > S_AXI_HP0_RRESP
Definition: design_1_processing_system7_0_0.sv:377
S_AXI_HP0_AWREADY
bit S_AXI_HP0_AWREADY
Definition: design_1_processing_system7_0_0.sv:371
DDR_ODT
bit DDR_ODT
Definition: design_1_processing_system7_0_0.sv:663
ENET0_MDIO_O
bit ENET0_MDIO_O
Definition: design_1_processing_system7_0_0.sv:12
M_AXI_GP0_RRESP
bit< 1 :0 > M_AXI_GP0_RRESP
Definition: design_1_processing_system7_0_0.sv:210
M_AXI_GP0_ARLOCK
bit< 1 :0 > M_AXI_GP0_ARLOCK
Definition: design_1_processing_system7_0_0.sv:183
ENET0_GMII_TXD
bit< 7 :0 > ENET0_GMII_TXD
Definition: design_1_processing_system7_0_0.sv:24
design_1_processing_system7_0_0_sc
Definition: design_1_processing_system7_0_0_sc.h:70
S_AXI_HP0_WSTRB
bit< 7 :0 > S_AXI_HP0_WSTRB
Definition: design_1_processing_system7_0_0.sv:414
ENET0_GMII_RXD
bit< 7 :0 > ENET0_GMII_RXD
Definition: design_1_processing_system7_0_0.sv:33
S_AXI_HP0_WLAST
bit S_AXI_HP0_WLAST
Definition: design_1_processing_system7_0_0.sv:391
DDR_VRN
bit DDR_VRN
Definition: design_1_processing_system7_0_0.sv:668
M_AXI_GP0_AWCACHE
bit< 3 :0 > M_AXI_GP0_AWCACHE
Definition: design_1_processing_system7_0_0.sv:196
design_1_processing_system7_0_0.h
S_AXI_HP0_AWPROT
bit< 2 :0 > S_AXI_HP0_AWPROT
Definition: design_1_processing_system7_0_0.sv:401
S_AXI_HP0_ARCACHE
bit< 3 :0 > S_AXI_HP0_ARCACHE
Definition: design_1_processing_system7_0_0.sv:404
ENET0_EXT_INTIN
bit ENET0_EXT_INTIN
Definition: design_1_processing_system7_0_0.sv:32
PS_CLK
bit PS_CLK
Definition: design_1_processing_system7_0_0.sv:675
ENET0_GMII_TX_EN
bit< 0 :0 > ENET0_GMII_TX_EN
Definition: design_1_processing_system7_0_0.sv:9
DDR_DM
bit< 3 :0 > DDR_DM
Definition: design_1_processing_system7_0_0.sv:670
ENET0_GMII_RX_ER
bit ENET0_GMII_RX_ER
Definition: design_1_processing_system7_0_0.sv:29
S_AXI_HP0_RACOUNT
bit< 2 :0 > S_AXI_HP0_RACOUNT
Definition: design_1_processing_system7_0_0.sv:383
S_AXI_HP0_RLAST
bit S_AXI_HP0_RLAST
Definition: design_1_processing_system7_0_0.sv:373
S_AXI_HP0_ARSIZE
bit< 2 :0 > S_AXI_HP0_ARSIZE
Definition: design_1_processing_system7_0_0.sv:396
ENET0_MDIO_MDC
bit ENET0_MDIO_MDC
Definition: design_1_processing_system7_0_0.sv:11
S_AXI_HP0_WACOUNT
bit< 5 :0 > S_AXI_HP0_WACOUNT
Definition: design_1_processing_system7_0_0.sv:384
M_AXI_GP0_AWLOCK
bit< 1 :0 > M_AXI_GP0_AWLOCK
Definition: design_1_processing_system7_0_0.sv:186
S_AXI_HP0_ARADDR
bit< 31 :0 > S_AXI_HP0_ARADDR
Definition: design_1_processing_system7_0_0.sv:402
S_AXI_HP0_AWSIZE
bit< 2 :0 > S_AXI_HP0_AWSIZE
Definition: design_1_processing_system7_0_0.sv:399
FCLK_CLK1
bit FCLK_CLK1
Definition: design_1_processing_system7_0_0.sv:617
M_AXI_GP0_AWLEN
bit< 3 :0 > M_AXI_GP0_AWLEN
Definition: design_1_processing_system7_0_0.sv:197
ENET0_GMII_CRS
bit ENET0_GMII_CRS
Definition: design_1_processing_system7_0_0.sv:26
M_AXI_GP0_RDATA
bit< 31 :0 > M_AXI_GP0_RDATA
Definition: design_1_processing_system7_0_0.sv:211
DDR_CKE
bit DDR_CKE
Definition: design_1_processing_system7_0_0.sv:658
S_AXI_HP0_AWVALID
bit S_AXI_HP0_AWVALID
Definition: design_1_processing_system7_0_0.sv:387
S_AXI_HP0_ARBURST
bit< 1 :0 > S_AXI_HP0_ARBURST
Definition: design_1_processing_system7_0_0.sv:394
S_AXI_HP0_ARLOCK
bit< 1 :0 > S_AXI_HP0_ARLOCK
Definition: design_1_processing_system7_0_0.sv:395
FCLK_CLK0
bit FCLK_CLK0
Definition: design_1_processing_system7_0_0.sv:616
FCLK_RESET0_N
bit FCLK_RESET0_N
Definition: design_1_processing_system7_0_0.sv:624
S_AXI_HP0_WREADY
bit S_AXI_HP0_WREADY
Definition: design_1_processing_system7_0_0.sv:375
S_AXI_HP0_ARQOS
bit< 3 :0 > S_AXI_HP0_ARQOS
Definition: design_1_processing_system7_0_0.sv:406
ENET0_GMII_COL
bit ENET0_GMII_COL
Definition: design_1_processing_system7_0_0.sv:25
M_AXI_GP0_AWSIZE
bit< 2 :0 > M_AXI_GP0_AWSIZE
Definition: design_1_processing_system7_0_0.sv:187
M_AXI_GP0_AWADDR
bit< 31 :0 > M_AXI_GP0_AWADDR
Definition: design_1_processing_system7_0_0.sv:191
M_AXI_GP0_AWID
bit< 11 :0 > M_AXI_GP0_AWID
Definition: design_1_processing_system7_0_0.sv:180
S_AXI_HP0_WID
bit< 5 :0 > S_AXI_HP0_WID
Definition: design_1_processing_system7_0_0.sv:412
processing_system7_v5_5_tlm.h
M_AXI_GP0_ARVALID
bit M_AXI_GP0_ARVALID
Definition: design_1_processing_system7_0_0.sv:173
S_AXI_HP0_RID
bit< 5 :0 > S_AXI_HP0_RID
Definition: design_1_processing_system7_0_0.sv:379
M_AXI_GP0_ARPROT
bit< 2 :0 > M_AXI_GP0_ARPROT
Definition: design_1_processing_system7_0_0.sv:188
S_AXI_HP0_BVALID
bit S_AXI_HP0_BVALID
Definition: design_1_processing_system7_0_0.sv:372
DDR_DQ
bit< 31 :0 > DDR_DQ
Definition: design_1_processing_system7_0_0.sv:671
S_AXI_HP0_AWADDR
bit< 31 :0 > S_AXI_HP0_AWADDR
Definition: design_1_processing_system7_0_0.sv:403
ENET0_GMII_TX_CLK
bit ENET0_GMII_TX_CLK
Definition: design_1_processing_system7_0_0.sv:30
FCLK_CLK3
bit FCLK_CLK3
Definition: design_1_processing_system7_0_0.sv:619
DDR_WEB
bit DDR_WEB
Definition: design_1_processing_system7_0_0.sv:665
M_AXI_GP0_ARQOS
bit< 3 :0 > M_AXI_GP0_ARQOS
Definition: design_1_processing_system7_0_0.sv:195
S_AXI_HP0_RREADY
bit S_AXI_HP0_RREADY
Definition: design_1_processing_system7_0_0.sv:390
M_AXI_GP0_AWREADY
bit M_AXI_GP0_AWREADY
Definition: design_1_processing_system7_0_0.sv:202
IRQ_F2P
bit< 0 :0 > IRQ_F2P
Definition: design_1_processing_system7_0_0.sv:579
PS_SRSTB
bit PS_SRSTB
Definition: design_1_processing_system7_0_0.sv:674
TTC0_WAVE0_OUT
bit TTC0_WAVE0_OUT
Definition: design_1_processing_system7_0_0.sv:148
TTC0_WAVE2_OUT
bit TTC0_WAVE2_OUT
Definition: design_1_processing_system7_0_0.sv:150
M_AXI_GP0_ARADDR
bit< 31 :0 > M_AXI_GP0_ARADDR
Definition: design_1_processing_system7_0_0.sv:190
M_AXI_GP0_ARCACHE
bit< 3 :0 > M_AXI_GP0_ARCACHE
Definition: design_1_processing_system7_0_0.sv:193
design_1_processing_system7_0_0
module design_1_processing_system7_0_0(ENET0_GMII_TX_EN, ENET0_GMII_TX_ER, ENET0_MDIO_MDC, ENET0_MDIO_O, ENET0_MDIO_T, ENET0_GMII_TXD, ENET0_GMII_COL, ENET0_GMII_CRS, ENET0_GMII_RX_CLK, ENET0_GMII_RX_DV, ENET0_GMII_RX_ER, ENET0_GMII_TX_CLK, ENET0_MDIO_I, ENET0_EXT_INTIN, ENET0_GMII_RXD, GPIO_I, GPIO_O, GPIO_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
Definition: design_1_processing_system7_0_0.sv:679
M_AXI_GP0_WVALID
bit M_AXI_GP0_WVALID
Definition: design_1_processing_system7_0_0.sv:178
ENET0_MDIO_I
bit ENET0_MDIO_I
Definition: design_1_processing_system7_0_0.sv:31
MIO
bit< 53 :0 > MIO
Definition: design_1_processing_system7_0_0.sv:656
GPIO_I
bit< 7 :0 > GPIO_I
Definition: design_1_processing_system7_0_0.sv:59
S_AXI_HP0_RVALID
bit S_AXI_HP0_RVALID
Definition: design_1_processing_system7_0_0.sv:374
ENET0_GMII_RX_DV
bit ENET0_GMII_RX_DV
Definition: design_1_processing_system7_0_0.sv:28
DDR_BankAddr
bit< 2 :0 > DDR_BankAddr
Definition: design_1_processing_system7_0_0.sv:666
PS_PORB
bit PS_PORB
Definition: design_1_processing_system7_0_0.sv:676
GPIO_O
bit< 7 :0 > GPIO_O
Definition: design_1_processing_system7_0_0.sv:60
S_AXI_HP0_WRISSUECAP1_EN
bit S_AXI_HP0_WRISSUECAP1_EN
Definition: design_1_processing_system7_0_0.sv:392
S_AXI_HP0_WDATA
bit< 63 :0 > S_AXI_HP0_WDATA
Definition: design_1_processing_system7_0_0.sv:413
S_AXI_HP0_BREADY
bit S_AXI_HP0_BREADY
Definition: design_1_processing_system7_0_0.sv:388
DDR_DQS
bit< 3 :0 > DDR_DQS
Definition: design_1_processing_system7_0_0.sv:673
S_AXI_HP0_RDISSUECAP1_EN
bit S_AXI_HP0_RDISSUECAP1_EN
Definition: design_1_processing_system7_0_0.sv:389
S_AXI_HP0_RCOUNT
bit< 7 :0 > S_AXI_HP0_RCOUNT
Definition: design_1_processing_system7_0_0.sv:381
M_AXI_GP0_WDATA
bit< 31 :0 > M_AXI_GP0_WDATA
Definition: design_1_processing_system7_0_0.sv:192
S_AXI_HP0_WCOUNT
bit< 7 :0 > S_AXI_HP0_WCOUNT
Definition: design_1_processing_system7_0_0.sv:382
M_AXI_GP0_BID
bit< 11 :0 > M_AXI_GP0_BID
Definition: design_1_processing_system7_0_0.sv:207
S_AXI_HP0_RDATA
bit< 63 :0 > S_AXI_HP0_RDATA
Definition: design_1_processing_system7_0_0.sv:380
M_AXI_GP0_WREADY
bit M_AXI_GP0_WREADY
Definition: design_1_processing_system7_0_0.sv:206
M_AXI_GP0_AWBURST
bit< 1 :0 > M_AXI_GP0_AWBURST
Definition: design_1_processing_system7_0_0.sv:185
M_AXI_GP0_ARREADY
bit M_AXI_GP0_ARREADY
Definition: design_1_processing_system7_0_0.sv:201
M_AXI_GP0_RID
bit< 11 :0 > M_AXI_GP0_RID
Definition: design_1_processing_system7_0_0.sv:208
ENET0_GMII_TX_ER
bit< 0 :0 > ENET0_GMII_TX_ER
Definition: design_1_processing_system7_0_0.sv:10
M_AXI_GP0_AWPROT
bit< 2 :0 > M_AXI_GP0_AWPROT
Definition: design_1_processing_system7_0_0.sv:189
ENET0_GMII_RX_CLK
bit ENET0_GMII_RX_CLK
Definition: design_1_processing_system7_0_0.sv:27
M_AXI_GP0_RREADY
bit M_AXI_GP0_RREADY
Definition: design_1_processing_system7_0_0.sv:176
S_AXI_HP0_ARID
bit< 5 :0 > S_AXI_HP0_ARID
Definition: design_1_processing_system7_0_0.sv:410
DDR_Clk
bit DDR_Clk
Definition: design_1_processing_system7_0_0.sv:660
DDR_Clk_n
bit DDR_Clk_n
Definition: design_1_processing_system7_0_0.sv:659
DDR_Addr
bit< 14 :0 > DDR_Addr
Definition: design_1_processing_system7_0_0.sv:667
M_AXI_GP0_WID
bit< 11 :0 > M_AXI_GP0_WID
Definition: design_1_processing_system7_0_0.sv:181
M_AXI_GP0_BRESP
bit< 1 :0 > M_AXI_GP0_BRESP
Definition: design_1_processing_system7_0_0.sv:209
M_AXI_GP0_RLAST
bit M_AXI_GP0_RLAST
Definition: design_1_processing_system7_0_0.sv:204
M_AXI_GP0_WLAST
bit M_AXI_GP0_WLAST
Definition: design_1_processing_system7_0_0.sv:177
S_AXI_HP0_ACLK
bit S_AXI_HP0_ACLK
Definition: design_1_processing_system7_0_0.sv:385
S_AXI_HP0_AWCACHE
bit< 3 :0 > S_AXI_HP0_AWCACHE
Definition: design_1_processing_system7_0_0.sv:407
M_AXI_GP0_ARBURST
bit< 1 :0 > M_AXI_GP0_ARBURST
Definition: design_1_processing_system7_0_0.sv:182
S_AXI_HP0_BRESP
bit< 1 :0 > S_AXI_HP0_BRESP
Definition: design_1_processing_system7_0_0.sv:376
DDR_DRSTB
bit DDR_DRSTB
Definition: design_1_processing_system7_0_0.sv:662
GPIO_T
bit< 7 :0 > GPIO_T
Definition: design_1_processing_system7_0_0.sv:61
S_AXI_HP0_AWQOS
bit< 3 :0 > S_AXI_HP0_AWQOS
Definition: design_1_processing_system7_0_0.sv:409
FCLK_CLK2
bit FCLK_CLK2
Definition: design_1_processing_system7_0_0.sv:618
S_AXI_HP0_ARREADY
bit S_AXI_HP0_ARREADY
Definition: design_1_processing_system7_0_0.sv:370
M_AXI_GP0_BREADY
bit M_AXI_GP0_BREADY
Definition: design_1_processing_system7_0_0.sv:175
M_AXI_GP0_ARSIZE
bit< 2 :0 > M_AXI_GP0_ARSIZE
Definition: design_1_processing_system7_0_0.sv:184
S_AXI_HP0_AWBURST
bit< 1 :0 > S_AXI_HP0_AWBURST
Definition: design_1_processing_system7_0_0.sv:397
M_AXI_GP0_ACLK
bit M_AXI_GP0_ACLK
Definition: design_1_processing_system7_0_0.sv:200
S_AXI_HP0_AWID
bit< 5 :0 > S_AXI_HP0_AWID
Definition: design_1_processing_system7_0_0.sv:411
DDR_CS_n
bit DDR_CS_n
Definition: design_1_processing_system7_0_0.sv:661
TTC0_WAVE1_OUT
bit TTC0_WAVE1_OUT
Definition: design_1_processing_system7_0_0.sv:149
M_AXI_GP0_ARLEN
bit< 3 :0 > M_AXI_GP0_ARLEN
Definition: design_1_processing_system7_0_0.sv:194
M_AXI_GP0_BVALID
bit M_AXI_GP0_BVALID
Definition: design_1_processing_system7_0_0.sv:203