10 reg [16:0] reset_timer = 0;
14 wire timer_expired = reset_timer > 16'd30000;
15 always @(posedge clk) reset_i <= timer_expired;
16 assign reset = reset_i;
19 always @(posedge clk) begin
20 if (usb_p_rx || usb_n_rx) begin
24 if (!timer_expired) begin
26 reset_timer <= reset_timer + 1;
module usb_reset_det(input clk, output reset, input usb_p_rx, input usb_n_rx)