vt52-fpga  1.0.0 Initial
vt52-fpga is a serial terminal implemented on a FPGA
usb_reset_det.v
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1 // detects USB port reset signal from host
2 module usb_reset_det (
3  input clk,
4  output reset,
5 
6  input usb_p_rx,
7  input usb_n_rx
8 );
9  // reset detection
10  reg [16:0] reset_timer = 0;
11  reg reset_i = 0;
12 
13 
14  wire timer_expired = reset_timer > 16'd30000;
15  always @(posedge clk) reset_i <= timer_expired;
16  assign reset = reset_i;
17 
18 
19  always @(posedge clk) begin
20  if (usb_p_rx || usb_n_rx) begin
21  reset_timer <= 0;
22  end else begin
23  // SE0 detected from host
24  if (!timer_expired) begin
25  // timer not expired yet, keep counting
26  reset_timer <= reset_timer + 1;
27  end
28  end
29  end
30 
31 endmodule
module usb_reset_det(input clk, output reset, input usb_p_rx, input usb_n_rx)
Definition: usb_reset_det.v:2
always(posedge clk)
Definition: uart_rx.v:86