3 parameter NUM_OUT_EPS = 1,
4 parameter MAX_OUT_PACKET_SIZE = 32
8 input [NUM_OUT_EPS-1:0] reset_ep,
14 output [NUM_OUT_EPS-1:0] out_ep_data_avail,
15 output reg [NUM_OUT_EPS-1:0] out_ep_setup = 0,
16 input [NUM_OUT_EPS-1:0] out_ep_data_get,
17 output reg [7:0] out_ep_data,
18 input [NUM_OUT_EPS-1:0] out_ep_stall,
19 output reg [NUM_OUT_EPS-1:0] out_ep_acked = 0,
21 input [NUM_OUT_EPS-1:0] out_ep_grant,
36 input [10:0] rx_frame_num,
48 output reg tx_pkt_start = 0,
50 output reg [3:0] tx_pid = 0
55 localparam READY_FOR_PKT = 0;
56 localparam PUTTING_PKT = 1;
57 localparam GETTING_PKT = 2;
60 reg [1:0] ep_state [NUM_OUT_EPS - 1:0];
61 reg [1:0] ep_state_next [NUM_OUT_EPS - 1:0];
68 localparam RCVD_OUT = 1;
69 localparam RCVD_DATA_START = 2;
70 localparam RCVD_DATA_END = 3;
72 reg [1:0] out_xfr_state = IDLE;
73 reg [1:0] out_xfr_state_next;
75 reg out_xfr_start = 0;
77 reg rollback_data = 0;
80 reg [3:0] out_ep_num = 0;
83 reg [NUM_OUT_EPS - 1:0] out_ep_data_avail_i = 0;
84 reg [NUM_OUT_EPS - 1:0] out_ep_data_avail_j = 0;
87 reg nak_out_transfer = 0;
90 reg [NUM_OUT_EPS - 1:0] data_toggle = 0;
93 reg [3:0] current_endp = 0;
94 wire [1:0] current_ep_state = ep_state[current_endp];
97 reg [7:0] out_data_buffer [(MAX_OUT_PACKET_SIZE * NUM_OUT_EPS) - 1:0];
100 reg [5:0] ep_get_addr [NUM_OUT_EPS - 1:0];
101 reg [5:0] ep_get_addr_next [NUM_OUT_EPS - 1:0];
105 reg [5:0] ep_put_addr [NUM_OUT_EPS - 1:0];
109 wire [8:0] buffer_put_addr = {current_endp[3:0], ep_put_addr[current_endp][4:0]};
110 wire [8:0] buffer_get_addr = {out_ep_num[3:0], ep_get_addr[out_ep_num][4:0]};
112 wire token_received =
115 rx_pid[1:0] == 2'b01 &&
116 rx_addr == dev_addr &&
117 rx_endp < NUM_OUT_EPS;
119 wire out_token_received =
121 rx_pid[3:2] == 2'b00;
123 wire setup_token_received =
125 rx_pid[3:2] == 2'b11;
127 wire invalid_packet_received =
131 wire data_packet_received =
134 rx_pid[2:0] == 3'b011;
136 wire non_data_packet_received =
139 rx_pid[2:0] != 3'b011;
143 wire bad_data_toggle =
144 data_packet_received &&
145 rx_pid[3] != data_toggle[rx_endp];
155 for (ep_num = 0; ep_num < NUM_OUT_EPS; ep_num = ep_num + 1) begin
158 ep_state_next[ep_num] <= ep_state[ep_num];
160 if (out_ep_stall[ep_num]) begin
161 ep_state_next[ep_num] <= STALL;
164 case (ep_state[ep_num])
165 READY_FOR_PKT : begin
166 if (out_xfr_start && rx_endp == ep_num) begin
167 ep_state_next[ep_num] <= PUTTING_PKT;
170 ep_state_next[ep_num] <= READY_FOR_PKT;
175 if (new_pkt_end && current_endp == ep_num) begin
176 ep_state_next[ep_num] <= GETTING_PKT;
178 end
else if (rollback_data && current_endp == ep_num) begin
179 ep_state_next[ep_num] <= READY_FOR_PKT;
182 ep_state_next[ep_num] <= PUTTING_PKT;
188 if (ep_get_addr[ep_num][5:0] >= (ep_put_addr[ep_num][5:0] - 6'H2)) begin
189 ep_state_next[ep_num] <= READY_FOR_PKT;
192 ep_state_next[ep_num] <= GETTING_PKT;
197 if (setup_token_received && rx_endp == ep_num) begin
198 ep_state_next[ep_num] <= READY_FOR_PKT;
201 ep_state_next[ep_num] <= STALL;
206 ep_state_next[ep_num] <= READY_FOR_PKT;
212 if (ep_state_next[ep_num][1:0] == READY_FOR_PKT) begin
213 ep_get_addr_next[ep_num][5:0] <= 0;
214 end
else if (ep_state_next[ep_num][1:0] == GETTING_PKT && out_ep_data_get[ep_num]) begin
215 ep_get_addr_next[ep_num][5:0] <= ep_get_addr[ep_num][5:0] + 6'H1;
217 ep_get_addr_next[ep_num][5:0] <= ep_get_addr[ep_num][5:0];
223 always @(posedge clk) begin
224 if (reset || reset_ep[ep_num]) begin
225 ep_state[ep_num] <= READY_FOR_PKT;
227 ep_state[ep_num] <= ep_state_next[ep_num];
230 ep_get_addr[ep_num][5:0] <= ep_get_addr_next[ep_num][5:0];
234 assign out_ep_data_avail[ep_num] =
235 (ep_get_addr[ep_num][5:0] < (ep_put_addr[ep_num][5:0] - 6'H2)) &&
236 (ep_state[ep_num][1:0] == GETTING_PKT);
244 always @(posedge clk) begin
249 if (setup_token_received) begin
250 out_ep_setup[rx_endp] <= 1;
251 end
else if (out_token_received) begin
252 out_ep_setup[rx_endp] <= 0;
256 for (i = 0; i < NUM_OUT_EPS; i = i + 1) begin
257 if (reset_ep[i]) begin
258 out_ep_setup[i] <= 0;
263 always @(posedge clk) out_ep_data <= out_data_buffer[buffer_get_addr][7:0];
265 integer ep_num_decoder;
269 for (ep_num_decoder = 0; ep_num_decoder < NUM_OUT_EPS; ep_num_decoder = ep_num_decoder + 1) begin
270 if (out_ep_grant[ep_num_decoder]) begin
271 out_ep_num <= ep_num_decoder;
283 out_xfr_state_next <= out_xfr_state;
291 if (out_token_received || setup_token_received) begin
292 out_xfr_state_next <= RCVD_OUT;
296 out_xfr_state_next <= IDLE;
301 if (rx_pkt_start) begin
302 out_xfr_state_next <= RCVD_DATA_START;
305 out_xfr_state_next <= RCVD_OUT;
309 RCVD_DATA_START : begin
310 if (bad_data_toggle) begin
311 out_xfr_state_next <= IDLE;
316 end
else if (invalid_packet_received || non_data_packet_received) begin
317 out_xfr_state_next <= IDLE;
320 end
else if (data_packet_received) begin
321 out_xfr_state_next <= RCVD_DATA_END;
324 out_xfr_state_next <= RCVD_DATA_START;
328 RCVD_DATA_END : begin
329 out_xfr_state_next <= IDLE;
332 if (ep_state[current_endp] == STALL) begin
335 end
else if (nak_out_transfer) begin
342 out_ep_acked[current_endp] <= 1;
351 out_xfr_state_next <= IDLE;
356 wire current_ep_busy =
357 (ep_state[current_endp] == GETTING_PKT) ||
358 (ep_state[current_endp] == READY_FOR_PKT);
361 always @(posedge clk) begin
363 out_xfr_state <= IDLE;
365 out_xfr_state <= out_xfr_state_next;
367 if (out_xfr_start) begin
368 current_endp <= rx_endp;
372 if (new_pkt_end) begin
373 data_toggle[current_endp] <= !data_toggle[current_endp];
376 if (setup_token_received) begin
377 data_toggle[rx_endp] <= 0;
385 if (current_ep_busy) begin
386 nak_out_transfer <= 1;
388 nak_out_transfer <= 0;
389 ep_put_addr[current_endp][5:0] <= 0;
393 RCVD_DATA_START : begin
394 if (!nak_out_transfer && rx_data_put && !ep_put_addr[current_endp][5]) begin
395 out_data_buffer[buffer_put_addr][7:0] <= rx_data;
398 if (!nak_out_transfer && rx_data_put) begin
399 ep_put_addr[current_endp][5:0] <= ep_put_addr[current_endp][5:0] + 6'H1;
404 RCVD_DATA_END : begin
409 for (j = 0; j < NUM_OUT_EPS; j = j + 1) begin
410 if (reset || reset_ep[j]) begin
412 ep_put_addr[j][5:0] <= 0;
module usb_fs_out_pe(input clk, input reset, input[NUM_OUT_EPS-1:0] reset_ep, input[7] dev_addr, output[NUM_OUT_EPS-1:0] out_ep_data_avail, output reg< NUM_OUT_EPS-1:0 > out_ep_setup=0, input[NUM_OUT_EPS-1:0] out_ep_data_get, output reg< 7:0 > out_ep_data, input[NUM_OUT_EPS-1:0] out_ep_stall, output reg< NUM_OUT_EPS-1:0 > out_ep_acked=0, input[NUM_OUT_EPS-1:0] out_ep_grant, input rx_pkt_start, input rx_pkt_end, input rx_pkt_valid, input[4] rx_pid, input[7] rx_addr, input[4] rx_endp, input[10:0] rx_frame_num, input rx_data_put, input[8] rx_data, output reg tx_pkt_start=0, input tx_pkt_end, output reg< 3:0 > tx_pid=0)