3 parameter NUM_IN_EPS = 11,
4 parameter MAX_IN_PACKET_SIZE = 32
8 input [NUM_IN_EPS-1:0] reset_ep,
15 output reg [NUM_IN_EPS-1:0] in_ep_data_free = 0,
16 input [NUM_IN_EPS-1:0] in_ep_data_put,
17 input [7:0] in_ep_data,
18 input [NUM_IN_EPS-1:0] in_ep_data_done,
19 input [NUM_IN_EPS-1:0] in_ep_stall,
20 output reg [NUM_IN_EPS-1:0] in_ep_acked = 0,
36 input [10:0] rx_frame_num,
44 output reg tx_pkt_start = 0,
49 output reg [3:0] tx_pid = 0,
54 output reg [7:0] tx_data,
62 reg [1:0] ep_state [NUM_IN_EPS - 1:0];
63 reg [1:0] ep_state_next [NUM_IN_EPS - 1:0];
66 reg [3:0] current_endp = 0;
68 wire [1:0] current_ep_state = ep_state[current_endp][1:0];
70 localparam READY_FOR_PKT = 0;
71 localparam PUTTING_PKT = 1;
72 localparam GETTING_PKT = 2;
75 assign debug[1:0] = ( current_endp == 1 ) ? current_ep_state : 0;
82 localparam RCVD_IN = 1;
83 localparam SEND_DATA = 2;
84 localparam WAIT_ACK = 3;
86 reg [1:0] in_xfr_state = IDLE;
87 reg [1:0] in_xfr_state_next;
89 assign debug[3:2] = ( current_endp == 1 ) ? in_xfr_state : 0;
94 assign debug[4] = tx_data_avail;
95 assign debug[5] = tx_data_get;
98 reg [NUM_IN_EPS - 1:0] data_toggle = 0;
101 reg [7:0] in_data_buffer [(MAX_IN_PACKET_SIZE * NUM_IN_EPS) - 1:0];
103 reg [5:0] ep_put_addr [NUM_IN_EPS - 1:0];
104 reg [5:0] ep_get_addr [NUM_IN_EPS - 1:0];
108 for (i = 0; i < NUM_IN_EPS; i = i + 1) begin
115 reg [3:0] in_ep_num = 0;
118 wire [8:0] buffer_put_addr = {in_ep_num[3:0], ep_put_addr[in_ep_num][4:0]};
119 wire [8:0] buffer_get_addr = {current_endp[3:0], ep_get_addr[current_endp][4:0]};
122 reg [NUM_IN_EPS - 1:0] endp_ready_to_send = 0;
125 reg [NUM_IN_EPS - 1:0] endp_free = 0;
127 wire token_received =
130 rx_pid[1:0] == 2'b01 &&
131 rx_addr == dev_addr &&
132 rx_endp < NUM_IN_EPS;
134 wire setup_token_received =
136 rx_pid[3:2] == 2'b11;
138 wire in_token_received =
140 rx_pid[3:2] == 2'b10;
147 assign debug[ 6 ] = rx_pkt_start;
148 assign debug[ 7 ] = rx_pkt_end;
151 wire more_data_to_send =
152 ep_get_addr[current_endp][5:0] < ep_put_addr[current_endp][5:0];
154 wire [5:0] current_ep_get_addr = ep_get_addr[current_endp][5:0];
155 wire [5:0] current_ep_put_addr = ep_put_addr[current_endp][5:0];
160 wire tx_data_avail_i =
161 in_xfr_state == SEND_DATA &&
164 assign tx_data_avail = tx_data_avail_i;
175 for (ep_num = 0; ep_num < NUM_IN_EPS; ep_num = ep_num + 1) begin
179 in_ep_acked[ep_num] <= 0;
181 ep_state_next[ep_num] <= ep_state[ep_num];
183 if (in_ep_stall[ep_num]) begin
184 ep_state_next[ep_num] <= STALL;
187 case (ep_state[ep_num])
188 READY_FOR_PKT : begin
189 ep_state_next[ep_num] <= PUTTING_PKT;
194 if ( ( in_ep_data_done[ep_num] ) || ( ep_put_addr[ep_num][5] ) ) begin
195 ep_state_next[ep_num] <= GETTING_PKT;
197 ep_state_next[ep_num] <= PUTTING_PKT;
204 if (in_xfr_end && current_endp == ep_num) begin
205 ep_state_next[ep_num] <= READY_FOR_PKT;
206 in_ep_acked[ep_num] <= 1;
209 ep_state_next[ep_num] <= GETTING_PKT;
214 if (setup_token_received && rx_endp == ep_num) begin
215 ep_state_next[ep_num] <= READY_FOR_PKT;
218 ep_state_next[ep_num] <= STALL;
223 ep_state_next[ep_num] <= READY_FOR_PKT;
228 endp_free[ep_num] = !ep_put_addr[ep_num][5];
229 in_ep_data_free[ep_num] = endp_free[ep_num] && ep_state[ep_num] == PUTTING_PKT;
233 always @(posedge clk) begin
234 if (reset || reset_ep[ep_num]) begin
235 ep_state[ep_num] <= READY_FOR_PKT;
238 ep_state[ep_num] <= ep_state_next[ep_num];
240 case (ep_state[ep_num])
241 READY_FOR_PKT : begin
243 ep_put_addr[ep_num][5:0] <= 0;
248 if (in_ep_data_put[ep_num] && ( ~ep_put_addr[ep_num][5] ) ) begin
249 ep_put_addr[ep_num][5:0] <= ep_put_addr[ep_num][5:0] + 1;
266 integer ep_num_decoder;
270 for (ep_num_decoder = 0; ep_num_decoder < NUM_IN_EPS; ep_num_decoder = ep_num_decoder + 1) begin
271 if (in_ep_data_put[ep_num_decoder]) begin
272 in_ep_num <= ep_num_decoder;
278 always @(posedge clk) begin
279 case (ep_state[in_ep_num])
281 if (in_ep_data_put[in_ep_num] && !ep_put_addr[in_ep_num][5]) begin
282 in_data_buffer[buffer_put_addr] <= in_ep_data;
296 in_xfr_state_next <= in_xfr_state;
301 rollback_in_xfr <= 0;
305 rollback_in_xfr <= 1;
307 if (in_token_received) begin
308 in_xfr_state_next <= RCVD_IN;
311 in_xfr_state_next <= IDLE;
319 if (ep_state[current_endp] == STALL) begin
320 in_xfr_state_next <= IDLE;
323 end
else if (ep_state[current_endp] == GETTING_PKT) begin
325 in_xfr_state_next <= SEND_DATA;
326 tx_pid <= {data_toggle[current_endp], 3'b011};
330 in_xfr_state_next <= IDLE;
337 if (!more_data_to_send) begin
338 in_xfr_state_next <= WAIT_ACK;
341 in_xfr_state_next <= SEND_DATA;
348 if (ack_received) begin
349 in_xfr_state_next <= IDLE;
352 end
else if (in_token_received) begin
353 in_xfr_state_next <= RCVD_IN;
354 rollback_in_xfr <= 1;
356 end
else if (rx_pkt_end) begin
357 in_xfr_state_next <= IDLE;
358 rollback_in_xfr <= 1;
361 in_xfr_state_next <= WAIT_ACK;
368 tx_data <= in_data_buffer[buffer_get_addr];
371 always @(posedge clk) begin
373 in_xfr_state <= IDLE;
376 in_xfr_state <= in_xfr_state_next;
380 if (setup_token_received) begin
381 data_toggle[rx_endp] <= 1;
384 if (in_token_received) begin
385 current_endp <= rx_endp;
388 if (rollback_in_xfr) begin
389 ep_get_addr[current_endp][5:0] <= 0;
400 if (tx_data_get && tx_data_avail_i) begin
401 ep_get_addr[current_endp][5:0] <= ep_get_addr[current_endp][5:0] + 1;
406 if (ack_received) begin
407 data_toggle[current_endp] <= !data_toggle[current_endp];
413 for (j = 0; j < NUM_IN_EPS; j = j + 1) begin
414 if (reset || reset_ep[j]) begin
416 ep_get_addr[j][5:0] <= 0;
module usb_fs_in_pe(input clk, input reset, input[NUM_IN_EPS-1:0] reset_ep, input[7] dev_addr, output reg< NUM_IN_EPS-1:0 > in_ep_data_free=0, input[NUM_IN_EPS-1:0] in_ep_data_put, input[8] in_ep_data, input[NUM_IN_EPS-1:0] in_ep_data_done, input[NUM_IN_EPS-1:0] in_ep_stall, output reg< NUM_IN_EPS-1:0 > in_ep_acked=0, input rx_pkt_start, input rx_pkt_end, input rx_pkt_valid, input[4] rx_pid, input[7] rx_addr, input[4] rx_endp, input[10:0] rx_frame_num, output reg tx_pkt_start=0, input tx_pkt_end, output reg< 3:0 > tx_pid=0, output tx_data_avail, input tx_data_get, output reg< 7:0 > tx_data, output[8] debug)