SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
axi_protocol_converter Class Reference

#include <axi_protocol_converter.h>

Inheritance diagram for axi_protocol_converter:
Collaboration diagram for axi_protocol_converter:

Public Member Functions

 axi_protocol_converter (sc_core::sc_module_name module_name, xsc::common_cpp::properties &)
 
virtual ~axi_protocol_converter ()
 
 SC_HAS_PROCESS (axi_protocol_converter)
 
 axi_protocol_converter (sc_core::sc_module_name module_name, xsc::common_cpp::properties &)
 
virtual ~axi_protocol_converter ()
 
 SC_HAS_PROCESS (axi_protocol_converter)
 

Public Attributes

xtlm::xtlm_aximm_target_socket * target_rd_socket
 
xtlm::xtlm_aximm_target_socket * target_wr_socket
 
xtlm::xtlm_aximm_initiator_socket * initiator_rd_socket
 
xtlm::xtlm_aximm_initiator_socket * initiator_wr_socket
 
sc_in< bool > aclk
 
sc_in< bool > aresetn
 

Private Attributes

xtlm::xtlm_aximm_passthru_module * P1
 
xtlm::xtlm_aximm_passthru_module * P2
 

Detailed Description

Constructor & Destructor Documentation

◆ axi_protocol_converter() [1/2]

axi_protocol_converter::axi_protocol_converter ( sc_core::sc_module_name  module_name,
xsc::common_cpp::properties &   
)

◆ ~axi_protocol_converter() [1/2]

axi_protocol_converter::~axi_protocol_converter ( )
virtual

◆ axi_protocol_converter() [2/2]

axi_protocol_converter::axi_protocol_converter ( sc_core::sc_module_name  module_name,
xsc::common_cpp::properties &   
)

◆ ~axi_protocol_converter() [2/2]

virtual axi_protocol_converter::~axi_protocol_converter ( )
virtual

Member Function Documentation

◆ SC_HAS_PROCESS() [1/2]

axi_protocol_converter::SC_HAS_PROCESS ( axi_protocol_converter  )

◆ SC_HAS_PROCESS() [2/2]

axi_protocol_converter::SC_HAS_PROCESS ( axi_protocol_converter  )

Member Data Documentation

◆ aclk

sc_in< bool > axi_protocol_converter::aclk

◆ aresetn

sc_in< bool > axi_protocol_converter::aresetn

◆ initiator_rd_socket

xtlm::xtlm_aximm_initiator_socket * axi_protocol_converter::initiator_rd_socket

◆ initiator_wr_socket

xtlm::xtlm_aximm_initiator_socket * axi_protocol_converter::initiator_wr_socket

◆ P1

xtlm::xtlm_aximm_passthru_module * axi_protocol_converter::P1
private

◆ P2

xtlm::xtlm_aximm_passthru_module * axi_protocol_converter::P2
private

◆ target_rd_socket

xtlm::xtlm_aximm_target_socket * axi_protocol_converter::target_rd_socket

◆ target_wr_socket

xtlm::xtlm_aximm_target_socket * axi_protocol_converter::target_wr_socket

The documentation for this class was generated from the following files: