SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_auto_pc_0/src/axi_protocol_converter.cpp
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2 #include <sstream>
3 
4 axi_protocol_converter::axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&) :
5  sc_module(module_name) {
6  initiator_rd_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_rd_socket",32);
7  initiator_wr_socket = new xtlm::xtlm_aximm_initiator_socket("initiator_wr_socket",32);
8  target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_rd_socket",32);
9  target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_wr_socket",32);
10  P1 = new xtlm::xtlm_aximm_passthru_module("P1");
11  P2 = new xtlm::xtlm_aximm_passthru_module("P2");
12  P1->initiator_socket->bind(*initiator_rd_socket);
13  P2->initiator_socket->bind(*initiator_wr_socket);
14  target_rd_socket->bind(*(P1->target_socket));
15  target_wr_socket->bind(*(P2->target_socket));
16  }
17 
19  delete initiator_wr_socket;
20  delete initiator_rd_socket;
21  delete target_wr_socket;
22  delete target_rd_socket;
23  delete P1;
24  delete P2;
25 }
axi_protocol_converter::initiator_wr_socket
xtlm::xtlm_aximm_initiator_socket * initiator_wr_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:15
axi_protocol_converter::axi_protocol_converter
axi_protocol_converter(sc_core::sc_module_name module_name, xsc::common_cpp::properties &)
Definition: design_1_auto_pc_0/src/axi_protocol_converter.cpp:4
axi_protocol_converter::initiator_rd_socket
xtlm::xtlm_aximm_initiator_socket * initiator_rd_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:14
axi_protocol_converter::target_rd_socket
xtlm::xtlm_aximm_target_socket * target_rd_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:12
axi_protocol_converter.h
axi_protocol_converter::P1
xtlm::xtlm_aximm_passthru_module * P1
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:19
axi_protocol_converter::~axi_protocol_converter
virtual ~axi_protocol_converter()
Definition: design_1_auto_pc_0/src/axi_protocol_converter.cpp:18
axi_protocol_converter::P2
xtlm::xtlm_aximm_passthru_module * P2
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:20
axi_protocol_converter::target_wr_socket
xtlm::xtlm_aximm_target_socket * target_wr_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:13