SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_auto_pc_1_sc.cpp
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48 
49 
50 #include "design_1_auto_pc_1_sc.h"
51 
52 #include "axi_protocol_converter.h"
53 
54 #include <map>
55 #include <string>
56 
57 design_1_auto_pc_1_sc::design_1_auto_pc_1_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
58 {
59  // configure connectivity manager
60  xsc::utils::xsc_sim_manager::addInstance("design_1_auto_pc_1", this);
61 
62  // initialize module
63  xsc::common_cpp::properties model_param_props;
64  model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
65  model_param_props.addLong("C_S_AXI_PROTOCOL", "1");
66  model_param_props.addLong("C_IGNORE_ID", "0");
67  model_param_props.addLong("C_AXI_ID_WIDTH", "12");
68  model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
69  model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
70  model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
71  model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
72  model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
73  model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
74  model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
75  model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
76  model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
77  model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
78  model_param_props.addLong("C_TRANSLATION_MODE", "2");
79  model_param_props.addString("C_FAMILY", "zynq");
80 
81  mp_impl = new axi_protocol_converter("inst", model_param_props);
82 
83  // initialize AXI sockets
88 }
89 
91 {
92  xsc::utils::xsc_sim_manager::clean();
93 
94  delete mp_impl;
95 }
96 
design_1_auto_pc_1_sc::design_1_auto_pc_1_sc
design_1_auto_pc_1_sc(const sc_core::sc_module_name &nm)
Definition: design_1_auto_pc_1_sc.cpp:57
design_1_auto_pc_1_sc::mp_impl
axi_protocol_converter * mp_impl
Definition: design_1_auto_pc_1_sc.h:89
design_1_auto_pc_1_sc::initiator_rd_socket
xtlm::xtlm_aximm_initiator_socket * initiator_rd_socket
Definition: design_1_auto_pc_1_sc.h:81
design_1_auto_pc_1_sc::target_wr_socket
xtlm::xtlm_aximm_target_socket * target_wr_socket
Definition: design_1_auto_pc_1_sc.h:80
axi_protocol_converter::initiator_wr_socket
xtlm::xtlm_aximm_initiator_socket * initiator_wr_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:15
design_1_auto_pc_1_sc::target_rd_socket
xtlm::xtlm_aximm_target_socket * target_rd_socket
Definition: design_1_auto_pc_1_sc.h:79
design_1_auto_pc_1_sc::~design_1_auto_pc_1_sc
virtual ~design_1_auto_pc_1_sc()
Definition: design_1_auto_pc_1_sc.cpp:90
axi_protocol_converter
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:7
design_1_auto_pc_1_sc::initiator_wr_socket
xtlm::xtlm_aximm_initiator_socket * initiator_wr_socket
Definition: design_1_auto_pc_1_sc.h:82
axi_protocol_converter::initiator_rd_socket
xtlm::xtlm_aximm_initiator_socket * initiator_rd_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:14
axi_protocol_converter::target_rd_socket
xtlm::xtlm_aximm_target_socket * target_rd_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:12
design_1_auto_pc_1_sc.h
axi_protocol_converter::target_wr_socket
xtlm::xtlm_aximm_target_socket * target_wr_socket
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:13