vt52-fpga  1.0.0 Initial
vt52-fpga is a serial terminal implemented on a FPGA
usb_uart_x7.v
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1 /*
2  usb_uart_x7
3 
4  Simple wrapper around the usb_uart which incorporates the Pin driver logic
5  so this doesn't clutter the top level circuit
6 
7  Make the signature generic (usb_uart) and rely on the file inclusion process (makefile)
8  to bring the correct architecture in
9 
10  The layer above has to assert the Host Pull Up line
11 
12  usb_uart u_u (
13  .clk_48mhz (clk_48mhz),
14  .reset (reset),
15 
16  // pins
17  .pin_usb_p( pin_usb_p ),
18  .pin_usb_n( pin_usb_n ),
19 
20  // uart pipeline in
21  .uart_in_data( uart_in_data ),
22  .uart_in_valid( uart_in_valid ),
23  .uart_in_ready( uart_in_ready ),
24 
25  // uart pipeline out
26  .uart_out_data( uart_out_data ),
27  .uart_out_valid( uart_out_valid ),
28  .uart_out_ready( uart_out_ready ),
29  );
30 
31 */
32 
33 //`include "../../pipe/rtl/pipe_defs.v"
34 
35 module usb_uart (
36  input clk_48mhz,
37  input reset,
38 
39  // USB pins
40  inout pin_usb_p,
41  inout pin_usb_n,
42 
43  // uart pipeline in (out of the device, into the host)
44  input [7:0] uart_in_data,
45  input uart_in_valid,
46  output uart_in_ready,
47 
48  // uart pipeline out (into the device, out of the host)
49  output [7:0] uart_out_data,
50  output uart_out_valid,
51  input uart_out_ready,
52 
53  output det_reset,
54  output [11:0] debug
55  );
56 
57 
58  // reset detection
59 /*
60  reg [16:0] reset_timer = 0;
61  reg reset_i = 0;
62 
63 
64  wire timer_expired = reset_timer > 16'd30000;
65  //wire timer_expired = reset_timer > 16'd30;
66  always @(posedge clk_48mhz) reset_i <= timer_expired;
67  assign reset_det = reset_i;
68 
69 
70  always @(posedge clk_48mhz) begin
71  if (usb_p_rx || usb_n_rx) begin
72  reset_timer <= 0;
73  end else begin
74  // SE0 detected from host
75  if (!timer_expired) begin
76  // timer not expired yet, keep counting
77  reset_timer <= reset_timer + 1;
78  end
79  end
80  end
81 */
82  wire usb_p_tx;
83  wire usb_n_tx;
84  wire usb_p_rx;
85  wire usb_n_rx;
86  wire usb_tx_en;
87 
88  //wire [3:0] debug;
89 
90 
92  .clk(clk_48mhz),
93  .reset(det_reset),
94  .usb_p_rx(usb_p_rx),
95  .usb_n_rx(usb_n_rx)
96  );
97 
98 
99 
100  usb_uart_core u_u_c_np (
101  .clk_48mhz (clk_48mhz),
102  .reset (reset || det_reset),
103 
104  // pins - these must be connected properly to the outside world. See below.
105  .usb_p_tx(usb_p_tx),
106  .usb_n_tx(usb_n_tx),
107  .usb_p_rx(usb_p_rx),
108  .usb_n_rx(usb_n_rx),
109  .usb_tx_en(usb_tx_en),
110 
111  // uart pipeline in
112  .uart_in_data( uart_in_data ),
113  .uart_in_valid( uart_in_valid ),
114  .uart_in_ready( uart_in_ready ),
115 
116  // uart pipeline out
117  .uart_out_data( uart_out_data ),
118  .uart_out_valid( uart_out_valid ),
119  .uart_out_ready( uart_out_ready ),
120 
121  .debug( debug )
122  );
123 
124  wire usb_p_in;
125  wire usb_n_in;
126 
127  assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
128  assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;
129 
130  IOBUF #(
131  .DRIVE(16), // Specify the output drive strength
132  .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
133  .IOSTANDARD("DEFAULT"), // Specify the I/O standard
134  .SLEW("FAST") // Specify the output slew rate
135  ) iobuf_p (
136  .O( usb_p_in ), // Buffer output
137  .I( usb_p_tx ), // Buffer input
138  .IO( pin_usb_p ), // Buffer inout port (connect directly to top-level port)
139  .T( !usb_tx_en ) // 3-state enable input, high=input, low=output
140  );
141 
142  IOBUF #(
143  .DRIVE(16), // Specify the output drive strength
144  .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
145  .IOSTANDARD("DEFAULT"), // Specify the I/O standard
146  .SLEW("FAST") // Specify the output slew rate
147  ) iobuf_n (
148  .O( usb_n_in ), // Buffer output
149  .I( usb_n_tx ), // Buffer input
150  .IO( pin_usb_n ), // Buffer inout port (connect directly to top-level port)
151  .T( !usb_tx_en ) // 3-state enable input, high=input, low=output
152  );
153 
154 endmodule
module usb_uart(input clk_48mhz, input reset, inout pin_usb_p, inout pin_usb_n, input[8] uart_in_data, input uart_in_valid, output uart_in_ready, output[8] uart_out_data, output uart_out_valid, input uart_out_ready, output det_reset, output[11:0] debug)
Definition: usb_uart_x7.v:35
module usb_uart_core(input clk_48mhz, input reset, output usb_p_tx, output usb_n_tx, input usb_p_rx, input usb_n_rx, output usb_tx_en, input[8] uart_in_data, input uart_in_valid, output uart_in_ready, output[8] uart_out_data, output uart_out_valid, input uart_out_ready, output[11:0] debug)
module usb_reset_det(input clk, output reset, input usb_p_rx, input usb_n_rx)
Definition: usb_reset_det.v:2