SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_xbar_0.h
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1 #ifndef IP_DESIGN_1_XBAR_0_H_
2 #define IP_DESIGN_1_XBAR_0_H_
3 
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51 
52 
53 #ifndef XTLM
54 #include "xtlm.h"
55 #endif
56 #ifndef SYSTEMC_INCLUDED
57 #include <systemc>
58 #endif
59 
60 #if defined(_MSC_VER)
61 #define DllExport __declspec(dllexport)
62 #elif defined(__GNUC__)
63 #define DllExport __attribute__ ((visibility("default")))
64 #else
65 #define DllExport
66 #endif
67 
68 #include "design_1_xbar_0_sc.h"
69 
70 
71 
72 
73 #ifdef XILINX_SIMULATOR
74 class DllExport design_1_xbar_0 : public design_1_xbar_0_sc
75 {
76 public:
77 
78  design_1_xbar_0(const sc_core::sc_module_name& nm);
79  virtual ~design_1_xbar_0();
80 
81  // module pin-to-pin RTL interface
82 
83  sc_core::sc_in< bool > aclk;
84  sc_core::sc_in< bool > aresetn;
85  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
86  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
87  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awvalid;
88  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_awready;
89  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
90  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
91  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wvalid;
92  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_wready;
93  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
94  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bvalid;
95  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_bready;
96  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
97  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
98  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arvalid;
99  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_arready;
100  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
101  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
102  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
103  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
104  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_awaddr;
105  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_awprot;
106  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awvalid;
107  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_awready;
108  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_wdata;
109  sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_wstrb;
110  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_wvalid;
111  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_wready;
112  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_bresp;
113  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_bvalid;
114  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_bready;
115  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_araddr;
116  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_arprot;
117  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arvalid;
118  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_arready;
119  sc_core::sc_in< sc_dt::sc_bv<96> > m_axi_rdata;
120  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_rresp;
121  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_rvalid;
122  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_rready;
123 
124  // Dummy Signals for IP Ports
125 
126 
127 protected:
128 
129  virtual void before_end_of_elaboration();
130 
131 private:
132 
133  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S00_AXI_transactor;
134  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awvalid_converter;
135  sc_signal< bool > m_s_axi_awvalid_converter_signal;
136  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_awready_converter;
137  sc_signal< bool > m_s_axi_awready_converter_signal;
138  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_wvalid_converter;
139  sc_signal< bool > m_s_axi_wvalid_converter_signal;
140  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_wready_converter;
141  sc_signal< bool > m_s_axi_wready_converter_signal;
142  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_bvalid_converter;
143  sc_signal< bool > m_s_axi_bvalid_converter_signal;
144  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_bready_converter;
145  sc_signal< bool > m_s_axi_bready_converter_signal;
146  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arvalid_converter;
147  sc_signal< bool > m_s_axi_arvalid_converter_signal;
148  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_arready_converter;
149  sc_signal< bool > m_s_axi_arready_converter_signal;
150  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_rvalid_converter;
151  sc_signal< bool > m_s_axi_rvalid_converter_signal;
152  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
153  sc_signal< bool > m_s_axi_rready_converter_signal;
154  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
155  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_0;
156  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
157  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_0;
158  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
159  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_0;
160  sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
161  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_0;
162  sc_signal< bool > m_m_axi_awready_converter_0_signal;
163  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_0;
164  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
165  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_0;
166  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
167  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_0;
168  sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
169  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_0;
170  sc_signal< bool > m_m_axi_wready_converter_0_signal;
171  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_0;
172  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
173  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_0;
174  sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
175  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_0;
176  sc_signal< bool > m_m_axi_bready_converter_0_signal;
177  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_0;
178  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
179  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_0;
180  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
181  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_0;
182  sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
183  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_0;
184  sc_signal< bool > m_m_axi_arready_converter_0_signal;
185  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_0;
186  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
187  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_0;
188  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
189  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_0;
190  sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
191  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_0;
192  sc_signal< bool > m_m_axi_rready_converter_0_signal;
193  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
194  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_1;
195  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
196  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_1;
197  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
198  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_1;
199  sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
200  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_1;
201  sc_signal< bool > m_m_axi_awready_converter_1_signal;
202  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_1;
203  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
204  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_1;
205  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
206  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_1;
207  sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
208  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_1;
209  sc_signal< bool > m_m_axi_wready_converter_1_signal;
210  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_1;
211  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
212  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_1;
213  sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
214  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_1;
215  sc_signal< bool > m_m_axi_bready_converter_1_signal;
216  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_1;
217  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
218  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_1;
219  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
220  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_1;
221  sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
222  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_1;
223  sc_signal< bool > m_m_axi_arready_converter_1_signal;
224  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_1;
225  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
226  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_1;
227  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
228  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_1;
229  sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
230  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_1;
231  sc_signal< bool > m_m_axi_rready_converter_1_signal;
232  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
233  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_2;
234  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
235  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_2;
236  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
237  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_2;
238  sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
239  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_2;
240  sc_signal< bool > m_m_axi_awready_converter_2_signal;
241  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_2;
242  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
243  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_2;
244  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
245  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_2;
246  sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
247  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_2;
248  sc_signal< bool > m_m_axi_wready_converter_2_signal;
249  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_2;
250  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
251  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_2;
252  sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
253  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_2;
254  sc_signal< bool > m_m_axi_bready_converter_2_signal;
255  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_2;
256  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
257  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_2;
258  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
259  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_2;
260  sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
261  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_2;
262  sc_signal< bool > m_m_axi_arready_converter_2_signal;
263  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_2;
264  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
265  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_2;
266  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
267  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_2;
268  sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
269  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_2;
270  sc_signal< bool > m_m_axi_rready_converter_2_signal;
271 
272  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_araddr;
273  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_0;
274  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_1;
275  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_2;
276 
277 
278 
279 
280 
281 
282  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_arprot;
283  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_0;
284  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_1;
285  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_2;
286 
287 
288  xsc::xsc_split<3, 3> * mp_m_axi_split_arready;
289  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_0;
290  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_1;
291  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_2;
292 
293 
294 
295 
296  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_arvalid;
297  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_0;
298  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_1;
299  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_2;
300 
301  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_awaddr;
302  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_0;
303  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_1;
304  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_2;
305 
306 
307 
308 
309 
310 
311  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_awprot;
312  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_0;
313  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_1;
314  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_2;
315 
316 
317  xsc::xsc_split<3, 3> * mp_m_axi_split_awready;
318  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_0;
319  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_1;
320  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_2;
321 
322 
323 
324 
325  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_awvalid;
326  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_0;
327  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_1;
328  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_2;
329 
330 
331  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_bready;
332  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_0;
333  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_1;
334  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_2;
335 
336  xsc::xsc_split<6, 3> * mp_m_axi_split_bresp;
337  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_0;
338  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_1;
339  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_2;
340 
341 
342  xsc::xsc_split<3, 3> * mp_m_axi_split_bvalid;
343  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_0;
344  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_1;
345  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_2;
346 
347  xsc::xsc_split<96, 3> * mp_m_axi_split_rdata;
348  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_0;
349  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_1;
350  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_2;
351 
352 
353 
354  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_rready;
355  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_0;
356  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_1;
357  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_2;
358 
359  xsc::xsc_split<6, 3> * mp_m_axi_split_rresp;
360  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_0;
361  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_1;
362  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_2;
363 
364 
365  xsc::xsc_split<3, 3> * mp_m_axi_split_rvalid;
366  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_0;
367  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_1;
368  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_2;
369 
370  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_wdata;
371  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_0;
372  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_1;
373  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_2;
374 
375 
376 
377  xsc::xsc_split<3, 3> * mp_m_axi_split_wready;
378  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_0;
379  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_1;
380  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_2;
381 
382  xsc::xsc_concatenator<12, 3> * mp_m_axi_concat_wstrb;
383  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_0;
384  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_1;
385  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_2;
386 
387 
388  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_wvalid;
389  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_0;
390  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_1;
391  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_2;
392 
393 };
394 #endif // XILINX_SIMULATOR
395 
396 
397 
398 
399 #ifdef XM_SYSTEMC
400 class DllExport design_1_xbar_0 : public design_1_xbar_0_sc
401 {
402 public:
403 
404  design_1_xbar_0(const sc_core::sc_module_name& nm);
405  virtual ~design_1_xbar_0();
406 
407  // module pin-to-pin RTL interface
408 
409  sc_core::sc_in< bool > aclk;
410  sc_core::sc_in< bool > aresetn;
411  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
412  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
413  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awvalid;
414  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_awready;
415  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
416  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
417  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wvalid;
418  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_wready;
419  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
420  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bvalid;
421  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_bready;
422  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
423  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
424  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arvalid;
425  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_arready;
426  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
427  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
428  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
429  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
430  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_awaddr;
431  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_awprot;
432  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awvalid;
433  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_awready;
434  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_wdata;
435  sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_wstrb;
436  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_wvalid;
437  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_wready;
438  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_bresp;
439  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_bvalid;
440  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_bready;
441  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_araddr;
442  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_arprot;
443  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arvalid;
444  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_arready;
445  sc_core::sc_in< sc_dt::sc_bv<96> > m_axi_rdata;
446  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_rresp;
447  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_rvalid;
448  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_rready;
449 
450  // Dummy Signals for IP Ports
451 
452 
453 protected:
454 
455  virtual void before_end_of_elaboration();
456 
457 private:
458 
459  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S00_AXI_transactor;
460  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awvalid_converter;
461  sc_signal< bool > m_s_axi_awvalid_converter_signal;
462  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_awready_converter;
463  sc_signal< bool > m_s_axi_awready_converter_signal;
464  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_wvalid_converter;
465  sc_signal< bool > m_s_axi_wvalid_converter_signal;
466  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_wready_converter;
467  sc_signal< bool > m_s_axi_wready_converter_signal;
468  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_bvalid_converter;
469  sc_signal< bool > m_s_axi_bvalid_converter_signal;
470  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_bready_converter;
471  sc_signal< bool > m_s_axi_bready_converter_signal;
472  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arvalid_converter;
473  sc_signal< bool > m_s_axi_arvalid_converter_signal;
474  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_arready_converter;
475  sc_signal< bool > m_s_axi_arready_converter_signal;
476  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_rvalid_converter;
477  sc_signal< bool > m_s_axi_rvalid_converter_signal;
478  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
479  sc_signal< bool > m_s_axi_rready_converter_signal;
480  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
481  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_0;
482  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
483  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_0;
484  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
485  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_0;
486  sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
487  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_0;
488  sc_signal< bool > m_m_axi_awready_converter_0_signal;
489  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_0;
490  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
491  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_0;
492  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
493  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_0;
494  sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
495  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_0;
496  sc_signal< bool > m_m_axi_wready_converter_0_signal;
497  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_0;
498  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
499  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_0;
500  sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
501  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_0;
502  sc_signal< bool > m_m_axi_bready_converter_0_signal;
503  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_0;
504  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
505  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_0;
506  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
507  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_0;
508  sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
509  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_0;
510  sc_signal< bool > m_m_axi_arready_converter_0_signal;
511  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_0;
512  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
513  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_0;
514  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
515  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_0;
516  sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
517  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_0;
518  sc_signal< bool > m_m_axi_rready_converter_0_signal;
519  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
520  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_1;
521  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
522  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_1;
523  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
524  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_1;
525  sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
526  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_1;
527  sc_signal< bool > m_m_axi_awready_converter_1_signal;
528  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_1;
529  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
530  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_1;
531  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
532  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_1;
533  sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
534  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_1;
535  sc_signal< bool > m_m_axi_wready_converter_1_signal;
536  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_1;
537  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
538  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_1;
539  sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
540  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_1;
541  sc_signal< bool > m_m_axi_bready_converter_1_signal;
542  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_1;
543  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
544  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_1;
545  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
546  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_1;
547  sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
548  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_1;
549  sc_signal< bool > m_m_axi_arready_converter_1_signal;
550  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_1;
551  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
552  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_1;
553  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
554  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_1;
555  sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
556  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_1;
557  sc_signal< bool > m_m_axi_rready_converter_1_signal;
558  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
559  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_2;
560  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
561  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_2;
562  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
563  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_2;
564  sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
565  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_2;
566  sc_signal< bool > m_m_axi_awready_converter_2_signal;
567  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_2;
568  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
569  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_2;
570  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
571  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_2;
572  sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
573  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_2;
574  sc_signal< bool > m_m_axi_wready_converter_2_signal;
575  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_2;
576  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
577  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_2;
578  sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
579  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_2;
580  sc_signal< bool > m_m_axi_bready_converter_2_signal;
581  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_2;
582  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
583  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_2;
584  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
585  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_2;
586  sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
587  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_2;
588  sc_signal< bool > m_m_axi_arready_converter_2_signal;
589  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_2;
590  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
591  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_2;
592  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
593  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_2;
594  sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
595  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_2;
596  sc_signal< bool > m_m_axi_rready_converter_2_signal;
597 
598  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_araddr;
599  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_0;
600  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_1;
601  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_2;
602 
603 
604 
605 
606 
607 
608  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_arprot;
609  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_0;
610  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_1;
611  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_2;
612 
613 
614  xsc::xsc_split<3, 3> * mp_m_axi_split_arready;
615  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_0;
616  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_1;
617  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_2;
618 
619 
620 
621 
622  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_arvalid;
623  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_0;
624  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_1;
625  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_2;
626 
627  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_awaddr;
628  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_0;
629  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_1;
630  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_2;
631 
632 
633 
634 
635 
636 
637  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_awprot;
638  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_0;
639  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_1;
640  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_2;
641 
642 
643  xsc::xsc_split<3, 3> * mp_m_axi_split_awready;
644  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_0;
645  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_1;
646  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_2;
647 
648 
649 
650 
651  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_awvalid;
652  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_0;
653  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_1;
654  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_2;
655 
656 
657  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_bready;
658  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_0;
659  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_1;
660  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_2;
661 
662  xsc::xsc_split<6, 3> * mp_m_axi_split_bresp;
663  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_0;
664  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_1;
665  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_2;
666 
667 
668  xsc::xsc_split<3, 3> * mp_m_axi_split_bvalid;
669  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_0;
670  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_1;
671  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_2;
672 
673  xsc::xsc_split<96, 3> * mp_m_axi_split_rdata;
674  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_0;
675  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_1;
676  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_2;
677 
678 
679 
680  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_rready;
681  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_0;
682  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_1;
683  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_2;
684 
685  xsc::xsc_split<6, 3> * mp_m_axi_split_rresp;
686  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_0;
687  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_1;
688  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_2;
689 
690 
691  xsc::xsc_split<3, 3> * mp_m_axi_split_rvalid;
692  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_0;
693  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_1;
694  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_2;
695 
696  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_wdata;
697  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_0;
698  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_1;
699  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_2;
700 
701 
702 
703  xsc::xsc_split<3, 3> * mp_m_axi_split_wready;
704  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_0;
705  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_1;
706  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_2;
707 
708  xsc::xsc_concatenator<12, 3> * mp_m_axi_concat_wstrb;
709  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_0;
710  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_1;
711  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_2;
712 
713 
714  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_wvalid;
715  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_0;
716  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_1;
717  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_2;
718 
719 };
720 #endif // XM_SYSTEMC
721 
722 
723 
724 
725 #ifdef RIVIERA
726 class DllExport design_1_xbar_0 : public design_1_xbar_0_sc
727 {
728 public:
729 
730  design_1_xbar_0(const sc_core::sc_module_name& nm);
731  virtual ~design_1_xbar_0();
732 
733  // module pin-to-pin RTL interface
734 
735  sc_core::sc_in< bool > aclk;
736  sc_core::sc_in< bool > aresetn;
737  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
738  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
739  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awvalid;
740  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_awready;
741  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
742  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
743  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wvalid;
744  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_wready;
745  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
746  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bvalid;
747  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_bready;
748  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
749  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
750  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arvalid;
751  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_arready;
752  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
753  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
754  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
755  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
756  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_awaddr;
757  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_awprot;
758  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awvalid;
759  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_awready;
760  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_wdata;
761  sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_wstrb;
762  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_wvalid;
763  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_wready;
764  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_bresp;
765  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_bvalid;
766  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_bready;
767  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_araddr;
768  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_arprot;
769  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arvalid;
770  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_arready;
771  sc_core::sc_in< sc_dt::sc_bv<96> > m_axi_rdata;
772  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_rresp;
773  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_rvalid;
774  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_rready;
775 
776  // Dummy Signals for IP Ports
777 
778 
779 protected:
780 
781  virtual void before_end_of_elaboration();
782 
783 private:
784 
785  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S00_AXI_transactor;
786  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awvalid_converter;
787  sc_signal< bool > m_s_axi_awvalid_converter_signal;
788  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_awready_converter;
789  sc_signal< bool > m_s_axi_awready_converter_signal;
790  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_wvalid_converter;
791  sc_signal< bool > m_s_axi_wvalid_converter_signal;
792  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_wready_converter;
793  sc_signal< bool > m_s_axi_wready_converter_signal;
794  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_bvalid_converter;
795  sc_signal< bool > m_s_axi_bvalid_converter_signal;
796  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_bready_converter;
797  sc_signal< bool > m_s_axi_bready_converter_signal;
798  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arvalid_converter;
799  sc_signal< bool > m_s_axi_arvalid_converter_signal;
800  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_arready_converter;
801  sc_signal< bool > m_s_axi_arready_converter_signal;
802  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_rvalid_converter;
803  sc_signal< bool > m_s_axi_rvalid_converter_signal;
804  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
805  sc_signal< bool > m_s_axi_rready_converter_signal;
806  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
807  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_0;
808  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
809  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_0;
810  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
811  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_0;
812  sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
813  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_0;
814  sc_signal< bool > m_m_axi_awready_converter_0_signal;
815  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_0;
816  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
817  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_0;
818  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
819  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_0;
820  sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
821  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_0;
822  sc_signal< bool > m_m_axi_wready_converter_0_signal;
823  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_0;
824  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
825  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_0;
826  sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
827  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_0;
828  sc_signal< bool > m_m_axi_bready_converter_0_signal;
829  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_0;
830  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
831  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_0;
832  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
833  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_0;
834  sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
835  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_0;
836  sc_signal< bool > m_m_axi_arready_converter_0_signal;
837  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_0;
838  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
839  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_0;
840  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
841  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_0;
842  sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
843  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_0;
844  sc_signal< bool > m_m_axi_rready_converter_0_signal;
845  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
846  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_1;
847  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
848  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_1;
849  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
850  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_1;
851  sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
852  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_1;
853  sc_signal< bool > m_m_axi_awready_converter_1_signal;
854  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_1;
855  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
856  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_1;
857  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
858  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_1;
859  sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
860  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_1;
861  sc_signal< bool > m_m_axi_wready_converter_1_signal;
862  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_1;
863  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
864  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_1;
865  sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
866  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_1;
867  sc_signal< bool > m_m_axi_bready_converter_1_signal;
868  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_1;
869  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
870  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_1;
871  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
872  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_1;
873  sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
874  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_1;
875  sc_signal< bool > m_m_axi_arready_converter_1_signal;
876  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_1;
877  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
878  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_1;
879  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
880  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_1;
881  sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
882  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_1;
883  sc_signal< bool > m_m_axi_rready_converter_1_signal;
884  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
885  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_2;
886  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
887  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_2;
888  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
889  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_2;
890  sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
891  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_2;
892  sc_signal< bool > m_m_axi_awready_converter_2_signal;
893  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_2;
894  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
895  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_2;
896  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
897  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_2;
898  sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
899  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_2;
900  sc_signal< bool > m_m_axi_wready_converter_2_signal;
901  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_2;
902  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
903  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_2;
904  sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
905  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_2;
906  sc_signal< bool > m_m_axi_bready_converter_2_signal;
907  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_2;
908  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
909  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_2;
910  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
911  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_2;
912  sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
913  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_2;
914  sc_signal< bool > m_m_axi_arready_converter_2_signal;
915  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_2;
916  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
917  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_2;
918  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
919  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_2;
920  sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
921  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_2;
922  sc_signal< bool > m_m_axi_rready_converter_2_signal;
923 
924  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_araddr;
925  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_0;
926  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_1;
927  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_2;
928 
929 
930 
931 
932 
933 
934  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_arprot;
935  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_0;
936  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_1;
937  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_2;
938 
939 
940  xsc::xsc_split<3, 3> * mp_m_axi_split_arready;
941  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_0;
942  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_1;
943  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_2;
944 
945 
946 
947 
948  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_arvalid;
949  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_0;
950  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_1;
951  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_2;
952 
953  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_awaddr;
954  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_0;
955  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_1;
956  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_2;
957 
958 
959 
960 
961 
962 
963  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_awprot;
964  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_0;
965  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_1;
966  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_2;
967 
968 
969  xsc::xsc_split<3, 3> * mp_m_axi_split_awready;
970  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_0;
971  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_1;
972  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_2;
973 
974 
975 
976 
977  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_awvalid;
978  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_0;
979  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_1;
980  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_2;
981 
982 
983  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_bready;
984  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_0;
985  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_1;
986  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_2;
987 
988  xsc::xsc_split<6, 3> * mp_m_axi_split_bresp;
989  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_0;
990  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_1;
991  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_2;
992 
993 
994  xsc::xsc_split<3, 3> * mp_m_axi_split_bvalid;
995  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_0;
996  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_1;
997  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_2;
998 
999  xsc::xsc_split<96, 3> * mp_m_axi_split_rdata;
1000  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_0;
1001  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_1;
1002  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_2;
1003 
1004 
1005 
1006  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_rready;
1007  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_0;
1008  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_1;
1009  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_2;
1010 
1011  xsc::xsc_split<6, 3> * mp_m_axi_split_rresp;
1012  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_0;
1013  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_1;
1014  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_2;
1015 
1016 
1017  xsc::xsc_split<3, 3> * mp_m_axi_split_rvalid;
1018  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_0;
1019  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_1;
1020  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_2;
1021 
1022  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_wdata;
1023  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_0;
1024  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_1;
1025  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_2;
1026 
1027 
1028 
1029  xsc::xsc_split<3, 3> * mp_m_axi_split_wready;
1030  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_0;
1031  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_1;
1032  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_2;
1033 
1034  xsc::xsc_concatenator<12, 3> * mp_m_axi_concat_wstrb;
1035  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_0;
1036  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_1;
1037  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_2;
1038 
1039 
1040  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_wvalid;
1041  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_0;
1042  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_1;
1043  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_2;
1044 
1045 };
1046 #endif // RIVIERA
1047 
1048 
1049 
1050 
1051 #ifdef VCSSYSTEMC
1052 #include "utils/xtlm_aximm_initiator_stub.h"
1053 
1054 #include "utils/xtlm_aximm_target_stub.h"
1055 
1056 class DllExport design_1_xbar_0 : public design_1_xbar_0_sc
1057 {
1058 public:
1059 
1060  design_1_xbar_0(const sc_core::sc_module_name& nm);
1061  virtual ~design_1_xbar_0();
1062 
1063  // module pin-to-pin RTL interface
1064 
1065  sc_core::sc_in< bool > aclk;
1066  sc_core::sc_in< bool > aresetn;
1067  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
1068  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
1069  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awvalid;
1070  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_awready;
1071  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
1072  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
1073  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wvalid;
1074  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_wready;
1075  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
1076  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bvalid;
1077  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_bready;
1078  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
1079  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
1080  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arvalid;
1081  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_arready;
1082  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
1083  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
1084  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
1085  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
1086  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_awaddr;
1087  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_awprot;
1088  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awvalid;
1089  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_awready;
1090  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_wdata;
1091  sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_wstrb;
1092  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_wvalid;
1093  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_wready;
1094  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_bresp;
1095  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_bvalid;
1096  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_bready;
1097  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_araddr;
1098  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_arprot;
1099  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arvalid;
1100  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_arready;
1101  sc_core::sc_in< sc_dt::sc_bv<96> > m_axi_rdata;
1102  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_rresp;
1103  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_rvalid;
1104  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_rready;
1105 
1106  // Dummy Signals for IP Ports
1107 
1108 
1109 protected:
1110 
1111  virtual void before_end_of_elaboration();
1112 
1113 private:
1114 
1115  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S00_AXI_transactor;
1116  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awvalid_converter;
1117  sc_signal< bool > m_s_axi_awvalid_converter_signal;
1118  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_awready_converter;
1119  sc_signal< bool > m_s_axi_awready_converter_signal;
1120  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_wvalid_converter;
1121  sc_signal< bool > m_s_axi_wvalid_converter_signal;
1122  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_wready_converter;
1123  sc_signal< bool > m_s_axi_wready_converter_signal;
1124  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_bvalid_converter;
1125  sc_signal< bool > m_s_axi_bvalid_converter_signal;
1126  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_bready_converter;
1127  sc_signal< bool > m_s_axi_bready_converter_signal;
1128  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arvalid_converter;
1129  sc_signal< bool > m_s_axi_arvalid_converter_signal;
1130  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_arready_converter;
1131  sc_signal< bool > m_s_axi_arready_converter_signal;
1132  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_rvalid_converter;
1133  sc_signal< bool > m_s_axi_rvalid_converter_signal;
1134  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
1135  sc_signal< bool > m_s_axi_rready_converter_signal;
1136  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
1137  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_0;
1138  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
1139  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_0;
1140  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
1141  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_0;
1142  sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
1143  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_0;
1144  sc_signal< bool > m_m_axi_awready_converter_0_signal;
1145  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_0;
1146  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
1147  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_0;
1148  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
1149  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_0;
1150  sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
1151  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_0;
1152  sc_signal< bool > m_m_axi_wready_converter_0_signal;
1153  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_0;
1154  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
1155  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_0;
1156  sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
1157  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_0;
1158  sc_signal< bool > m_m_axi_bready_converter_0_signal;
1159  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_0;
1160  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
1161  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_0;
1162  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
1163  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_0;
1164  sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
1165  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_0;
1166  sc_signal< bool > m_m_axi_arready_converter_0_signal;
1167  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_0;
1168  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
1169  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_0;
1170  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
1171  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_0;
1172  sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
1173  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_0;
1174  sc_signal< bool > m_m_axi_rready_converter_0_signal;
1175  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
1176  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_1;
1177  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
1178  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_1;
1179  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
1180  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_1;
1181  sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
1182  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_1;
1183  sc_signal< bool > m_m_axi_awready_converter_1_signal;
1184  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_1;
1185  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
1186  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_1;
1187  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
1188  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_1;
1189  sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
1190  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_1;
1191  sc_signal< bool > m_m_axi_wready_converter_1_signal;
1192  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_1;
1193  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
1194  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_1;
1195  sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
1196  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_1;
1197  sc_signal< bool > m_m_axi_bready_converter_1_signal;
1198  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_1;
1199  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
1200  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_1;
1201  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
1202  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_1;
1203  sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
1204  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_1;
1205  sc_signal< bool > m_m_axi_arready_converter_1_signal;
1206  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_1;
1207  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
1208  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_1;
1209  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
1210  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_1;
1211  sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
1212  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_1;
1213  sc_signal< bool > m_m_axi_rready_converter_1_signal;
1214  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
1215  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_2;
1216  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
1217  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_2;
1218  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
1219  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_2;
1220  sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
1221  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_2;
1222  sc_signal< bool > m_m_axi_awready_converter_2_signal;
1223  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_2;
1224  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
1225  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_2;
1226  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
1227  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_2;
1228  sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
1229  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_2;
1230  sc_signal< bool > m_m_axi_wready_converter_2_signal;
1231  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_2;
1232  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
1233  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_2;
1234  sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
1235  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_2;
1236  sc_signal< bool > m_m_axi_bready_converter_2_signal;
1237  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_2;
1238  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
1239  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_2;
1240  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
1241  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_2;
1242  sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
1243  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_2;
1244  sc_signal< bool > m_m_axi_arready_converter_2_signal;
1245  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_2;
1246  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
1247  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_2;
1248  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
1249  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_2;
1250  sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
1251  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_2;
1252  sc_signal< bool > m_m_axi_rready_converter_2_signal;
1253 
1254  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_araddr;
1255  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_0;
1256  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_1;
1257  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_2;
1258 
1259 
1260 
1261 
1262 
1263 
1264  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_arprot;
1265  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_0;
1266  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_1;
1267  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_2;
1268 
1269 
1270  xsc::xsc_split<3, 3> * mp_m_axi_split_arready;
1271  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_0;
1272  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_1;
1273  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_2;
1274 
1275 
1276 
1277 
1278  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_arvalid;
1279  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_0;
1280  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_1;
1281  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_2;
1282 
1283  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_awaddr;
1284  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_0;
1285  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_1;
1286  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_2;
1287 
1288 
1289 
1290 
1291 
1292 
1293  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_awprot;
1294  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_0;
1295  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_1;
1296  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_2;
1297 
1298 
1299  xsc::xsc_split<3, 3> * mp_m_axi_split_awready;
1300  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_0;
1301  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_1;
1302  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_2;
1303 
1304 
1305 
1306 
1307  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_awvalid;
1308  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_0;
1309  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_1;
1310  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_2;
1311 
1312 
1313  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_bready;
1314  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_0;
1315  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_1;
1316  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_2;
1317 
1318  xsc::xsc_split<6, 3> * mp_m_axi_split_bresp;
1319  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_0;
1320  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_1;
1321  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_2;
1322 
1323 
1324  xsc::xsc_split<3, 3> * mp_m_axi_split_bvalid;
1325  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_0;
1326  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_1;
1327  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_2;
1328 
1329  xsc::xsc_split<96, 3> * mp_m_axi_split_rdata;
1330  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_0;
1331  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_1;
1332  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_2;
1333 
1334 
1335 
1336  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_rready;
1337  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_0;
1338  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_1;
1339  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_2;
1340 
1341  xsc::xsc_split<6, 3> * mp_m_axi_split_rresp;
1342  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_0;
1343  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_1;
1344  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_2;
1345 
1346 
1347  xsc::xsc_split<3, 3> * mp_m_axi_split_rvalid;
1348  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_0;
1349  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_1;
1350  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_2;
1351 
1352  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_wdata;
1353  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_0;
1354  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_1;
1355  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_2;
1356 
1357 
1358 
1359  xsc::xsc_split<3, 3> * mp_m_axi_split_wready;
1360  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_0;
1361  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_1;
1362  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_2;
1363 
1364  xsc::xsc_concatenator<12, 3> * mp_m_axi_concat_wstrb;
1365  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_0;
1366  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_1;
1367  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_2;
1368 
1369 
1370  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_wvalid;
1371  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_0;
1372  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_1;
1373  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_2;
1374 
1375  // Transactor stubs
1376  xtlm::xtlm_aximm_initiator_stub * M00_AXI_transactor_initiator_rd_socket_stub;
1377  xtlm::xtlm_aximm_initiator_stub * M00_AXI_transactor_initiator_wr_socket_stub;
1378  xtlm::xtlm_aximm_initiator_stub * M01_AXI_transactor_initiator_rd_socket_stub;
1379  xtlm::xtlm_aximm_initiator_stub * M01_AXI_transactor_initiator_wr_socket_stub;
1380  xtlm::xtlm_aximm_initiator_stub * M02_AXI_transactor_initiator_rd_socket_stub;
1381  xtlm::xtlm_aximm_initiator_stub * M02_AXI_transactor_initiator_wr_socket_stub;
1382  xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_rd_socket_stub;
1383  xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_wr_socket_stub;
1384 
1385  // Socket stubs
1386 
1387 };
1388 #endif // VCSSYSTEMC
1389 
1390 
1391 
1392 
1393 #ifdef MTI_SYSTEMC
1394 #include "utils/xtlm_aximm_initiator_stub.h"
1395 
1396 #include "utils/xtlm_aximm_target_stub.h"
1397 
1398 class DllExport design_1_xbar_0 : public design_1_xbar_0_sc
1399 {
1400 public:
1401 
1402  design_1_xbar_0(const sc_core::sc_module_name& nm);
1403  virtual ~design_1_xbar_0();
1404 
1405  // module pin-to-pin RTL interface
1406 
1407  sc_core::sc_in< bool > aclk;
1408  sc_core::sc_in< bool > aresetn;
1409  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
1410  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
1411  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awvalid;
1412  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_awready;
1413  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
1414  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
1415  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wvalid;
1416  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_wready;
1417  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
1418  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bvalid;
1419  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_bready;
1420  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
1421  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
1422  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arvalid;
1423  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_arready;
1424  sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
1425  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
1426  sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
1427  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
1428  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_awaddr;
1429  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_awprot;
1430  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awvalid;
1431  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_awready;
1432  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_wdata;
1433  sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_wstrb;
1434  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_wvalid;
1435  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_wready;
1436  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_bresp;
1437  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_bvalid;
1438  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_bready;
1439  sc_core::sc_out< sc_dt::sc_bv<96> > m_axi_araddr;
1440  sc_core::sc_out< sc_dt::sc_bv<9> > m_axi_arprot;
1441  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arvalid;
1442  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_arready;
1443  sc_core::sc_in< sc_dt::sc_bv<96> > m_axi_rdata;
1444  sc_core::sc_in< sc_dt::sc_bv<6> > m_axi_rresp;
1445  sc_core::sc_in< sc_dt::sc_bv<3> > m_axi_rvalid;
1446  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_rready;
1447 
1448  // Dummy Signals for IP Ports
1449 
1450 
1451 protected:
1452 
1453  virtual void before_end_of_elaboration();
1454 
1455 private:
1456 
1457  xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S00_AXI_transactor;
1458  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_awvalid_converter;
1459  sc_signal< bool > m_s_axi_awvalid_converter_signal;
1460  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_awready_converter;
1461  sc_signal< bool > m_s_axi_awready_converter_signal;
1462  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_wvalid_converter;
1463  sc_signal< bool > m_s_axi_wvalid_converter_signal;
1464  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_wready_converter;
1465  sc_signal< bool > m_s_axi_wready_converter_signal;
1466  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_bvalid_converter;
1467  sc_signal< bool > m_s_axi_bvalid_converter_signal;
1468  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_bready_converter;
1469  sc_signal< bool > m_s_axi_bready_converter_signal;
1470  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arvalid_converter;
1471  sc_signal< bool > m_s_axi_arvalid_converter_signal;
1472  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_arready_converter;
1473  sc_signal< bool > m_s_axi_arready_converter_signal;
1474  xsc::common::scalar2vectorN_converter<1>* mp_s_axi_rvalid_converter;
1475  sc_signal< bool > m_s_axi_rvalid_converter_signal;
1476  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
1477  sc_signal< bool > m_s_axi_rready_converter_signal;
1478  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
1479  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_0;
1480  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
1481  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_0;
1482  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
1483  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_0;
1484  sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
1485  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_0;
1486  sc_signal< bool > m_m_axi_awready_converter_0_signal;
1487  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_0;
1488  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
1489  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_0;
1490  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
1491  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_0;
1492  sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
1493  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_0;
1494  sc_signal< bool > m_m_axi_wready_converter_0_signal;
1495  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_0;
1496  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
1497  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_0;
1498  sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
1499  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_0;
1500  sc_signal< bool > m_m_axi_bready_converter_0_signal;
1501  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_0;
1502  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
1503  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_0;
1504  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
1505  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_0;
1506  sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
1507  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_0;
1508  sc_signal< bool > m_m_axi_arready_converter_0_signal;
1509  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_0;
1510  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
1511  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_0;
1512  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
1513  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_0;
1514  sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
1515  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_0;
1516  sc_signal< bool > m_m_axi_rready_converter_0_signal;
1517  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
1518  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_1;
1519  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
1520  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_1;
1521  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
1522  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_1;
1523  sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
1524  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_1;
1525  sc_signal< bool > m_m_axi_awready_converter_1_signal;
1526  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_1;
1527  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
1528  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_1;
1529  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
1530  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_1;
1531  sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
1532  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_1;
1533  sc_signal< bool > m_m_axi_wready_converter_1_signal;
1534  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_1;
1535  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
1536  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_1;
1537  sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
1538  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_1;
1539  sc_signal< bool > m_m_axi_bready_converter_1_signal;
1540  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_1;
1541  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
1542  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_1;
1543  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
1544  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_1;
1545  sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
1546  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_1;
1547  sc_signal< bool > m_m_axi_arready_converter_1_signal;
1548  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_1;
1549  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
1550  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_1;
1551  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
1552  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_1;
1553  sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
1554  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_1;
1555  sc_signal< bool > m_m_axi_rready_converter_1_signal;
1556  xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
1557  xsc::common::vector2vector_converter<32,96>* mp_m_axi_awaddr_converter_2;
1558  sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
1559  xsc::common::vector2vector_converter<3,9>* mp_m_axi_awprot_converter_2;
1560  sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
1561  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_awvalid_converter_2;
1562  sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
1563  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_awready_converter_2;
1564  sc_signal< bool > m_m_axi_awready_converter_2_signal;
1565  xsc::common::vector2vector_converter<32,96>* mp_m_axi_wdata_converter_2;
1566  sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
1567  xsc::common::vector2vector_converter<4,12>* mp_m_axi_wstrb_converter_2;
1568  sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
1569  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_wvalid_converter_2;
1570  sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
1571  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_wready_converter_2;
1572  sc_signal< bool > m_m_axi_wready_converter_2_signal;
1573  xsc::common::vector2vector_converter<6,2>* mp_m_axi_bresp_converter_2;
1574  sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
1575  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_bvalid_converter_2;
1576  sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
1577  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_bready_converter_2;
1578  sc_signal< bool > m_m_axi_bready_converter_2_signal;
1579  xsc::common::vector2vector_converter<32,96>* mp_m_axi_araddr_converter_2;
1580  sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
1581  xsc::common::vector2vector_converter<3,9>* mp_m_axi_arprot_converter_2;
1582  sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
1583  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_arvalid_converter_2;
1584  sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
1585  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_arready_converter_2;
1586  sc_signal< bool > m_m_axi_arready_converter_2_signal;
1587  xsc::common::vector2vector_converter<96,32>* mp_m_axi_rdata_converter_2;
1588  sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
1589  xsc::common::vector2vector_converter<6,2>* mp_m_axi_rresp_converter_2;
1590  sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
1591  xsc::common::vectorN2scalar_converter<3>* mp_m_axi_rvalid_converter_2;
1592  sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
1593  xsc::common::scalar2vectorN_converter<3>* mp_m_axi_rready_converter_2;
1594  sc_signal< bool > m_m_axi_rready_converter_2_signal;
1595 
1596  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_araddr;
1597  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_0;
1598  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_1;
1599  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_araddr_out_2;
1600 
1601 
1602 
1603 
1604 
1605 
1606  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_arprot;
1607  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_0;
1608  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_1;
1609  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_arprot_out_2;
1610 
1611 
1612  xsc::xsc_split<3, 3> * mp_m_axi_split_arready;
1613  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_0;
1614  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_1;
1615  sc_signal<sc_dt::sc_bv<3> > m_axi_split_arready_out_2;
1616 
1617 
1618 
1619 
1620  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_arvalid;
1621  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_0;
1622  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_1;
1623  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_arvalid_out_2;
1624 
1625  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_awaddr;
1626  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_0;
1627  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_1;
1628  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_awaddr_out_2;
1629 
1630 
1631 
1632 
1633 
1634 
1635  xsc::xsc_concatenator<9, 3> * mp_m_axi_concat_awprot;
1636  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_0;
1637  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_1;
1638  sc_signal<sc_dt::sc_bv<9> > m_axi_concat_awprot_out_2;
1639 
1640 
1641  xsc::xsc_split<3, 3> * mp_m_axi_split_awready;
1642  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_0;
1643  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_1;
1644  sc_signal<sc_dt::sc_bv<3> > m_axi_split_awready_out_2;
1645 
1646 
1647 
1648 
1649  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_awvalid;
1650  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_0;
1651  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_1;
1652  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_awvalid_out_2;
1653 
1654 
1655  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_bready;
1656  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_0;
1657  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_1;
1658  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_bready_out_2;
1659 
1660  xsc::xsc_split<6, 3> * mp_m_axi_split_bresp;
1661  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_0;
1662  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_1;
1663  sc_signal<sc_dt::sc_bv<6> > m_axi_split_bresp_out_2;
1664 
1665 
1666  xsc::xsc_split<3, 3> * mp_m_axi_split_bvalid;
1667  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_0;
1668  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_1;
1669  sc_signal<sc_dt::sc_bv<3> > m_axi_split_bvalid_out_2;
1670 
1671  xsc::xsc_split<96, 3> * mp_m_axi_split_rdata;
1672  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_0;
1673  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_1;
1674  sc_signal<sc_dt::sc_bv<96> > m_axi_split_rdata_out_2;
1675 
1676 
1677 
1678  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_rready;
1679  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_0;
1680  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_1;
1681  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_rready_out_2;
1682 
1683  xsc::xsc_split<6, 3> * mp_m_axi_split_rresp;
1684  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_0;
1685  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_1;
1686  sc_signal<sc_dt::sc_bv<6> > m_axi_split_rresp_out_2;
1687 
1688 
1689  xsc::xsc_split<3, 3> * mp_m_axi_split_rvalid;
1690  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_0;
1691  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_1;
1692  sc_signal<sc_dt::sc_bv<3> > m_axi_split_rvalid_out_2;
1693 
1694  xsc::xsc_concatenator<96, 3> * mp_m_axi_concat_wdata;
1695  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_0;
1696  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_1;
1697  sc_signal<sc_dt::sc_bv<96> > m_axi_concat_wdata_out_2;
1698 
1699 
1700 
1701  xsc::xsc_split<3, 3> * mp_m_axi_split_wready;
1702  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_0;
1703  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_1;
1704  sc_signal<sc_dt::sc_bv<3> > m_axi_split_wready_out_2;
1705 
1706  xsc::xsc_concatenator<12, 3> * mp_m_axi_concat_wstrb;
1707  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_0;
1708  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_1;
1709  sc_signal<sc_dt::sc_bv<12> > m_axi_concat_wstrb_out_2;
1710 
1711 
1712  xsc::xsc_concatenator<3, 3> * mp_m_axi_concat_wvalid;
1713  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_0;
1714  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_1;
1715  sc_signal<sc_dt::sc_bv<3> > m_axi_concat_wvalid_out_2;
1716 
1717  // Transactor stubs
1718  xtlm::xtlm_aximm_initiator_stub * M00_AXI_transactor_initiator_rd_socket_stub;
1719  xtlm::xtlm_aximm_initiator_stub * M00_AXI_transactor_initiator_wr_socket_stub;
1720  xtlm::xtlm_aximm_initiator_stub * M01_AXI_transactor_initiator_rd_socket_stub;
1721  xtlm::xtlm_aximm_initiator_stub * M01_AXI_transactor_initiator_wr_socket_stub;
1722  xtlm::xtlm_aximm_initiator_stub * M02_AXI_transactor_initiator_rd_socket_stub;
1723  xtlm::xtlm_aximm_initiator_stub * M02_AXI_transactor_initiator_wr_socket_stub;
1724  xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_rd_socket_stub;
1725  xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_wr_socket_stub;
1726 
1727  // Socket stubs
1728 
1729 };
1730 #endif // MTI_SYSTEMC
1731 #endif // IP_DESIGN_1_XBAR_0_H_
s_axi_awready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire s_axi_awready
Definition: axi_vip_v1_1_vl_rfs.sv:109
s_axi_bready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire s_axi_bready
Definition: axi_vip_v1_1_vl_rfs.sv:125
design_1_xbar_0_sc
Definition: design_1_xbar_0_sc.h:70
m_axi_wdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > m_axi_wdata
Definition: axi_vip_v1_1_vl_rfs.sv:168
m_axi_wvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire m_axi_wvalid
Definition: axi_vip_v1_1_vl_rfs.sv:172
m_axi_bvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire m_axi_bvalid
Definition: axi_vip_v1_1_vl_rfs.sv:179
s_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire s_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:148
DllExport
#define DllExport
Definition: design_1_xbar_0.h:65
m_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire m_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:195
m_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire m_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:203
s_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire s_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:149
s_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire s_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:139
s_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > s_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:145
s_axi_bresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > s_axi_bresp
Definition: axi_vip_v1_1_vl_rfs.sv:122
s_axi_awprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > s_axi_awprot
Definition: axi_vip_v1_1_vl_rfs.sv:104
s_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire s_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:140
s_axi_wdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > s_axi_wdata
Definition: axi_vip_v1_1_vl_rfs.sv:113
m_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire output wire m_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:205
m_axi_awaddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > m_axi_awaddr
Definition: axi_vip_v1_1_vl_rfs.sv:153
s_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > s_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:129
s_axi_awaddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > s_axi_awaddr
Definition: axi_vip_v1_1_vl_rfs.sv:98
m_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > m_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:200
m_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire m_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:194
s_axi_wstrb
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > s_axi_wstrb
Definition: axi_vip_v1_1_vl_rfs.sv:114
aresetn
DowngradeIPIdentifiedWarnings module input wire input wire aresetn
Definition: axi_vip_v1_1_vl_rfs.sv:94
design_1_xbar_0_sc.h
s_axi_awvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire s_axi_awvalid
Definition: axi_vip_v1_1_vl_rfs.sv:108
s_axi_wready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire s_axi_wready
Definition: axi_vip_v1_1_vl_rfs.sv:118
m_axi_bresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > m_axi_bresp
Definition: axi_vip_v1_1_vl_rfs.sv:177
m_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > m_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:199
m_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > m_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:184
m_axi_awvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire m_axi_awvalid
Definition: axi_vip_v1_1_vl_rfs.sv:163
m_axi_bready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire m_axi_bready
Definition: axi_vip_v1_1_vl_rfs.sv:180
s_axi_wvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire s_axi_wvalid
Definition: axi_vip_v1_1_vl_rfs.sv:117
m_axi_wready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire m_axi_wready
Definition: axi_vip_v1_1_vl_rfs.sv:173
m_axi_awready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire m_axi_awready
Definition: axi_vip_v1_1_vl_rfs.sv:164
m_axi_awprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > m_axi_awprot
Definition: axi_vip_v1_1_vl_rfs.sv:159
m_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > m_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:190
s_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > s_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:144
m_axi_wstrb
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > m_axi_wstrb
Definition: axi_vip_v1_1_vl_rfs.sv:169
s_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > s_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:135
s_axi_bvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire s_axi_bvalid
Definition: axi_vip_v1_1_vl_rfs.sv:124