axi_vip_v1_1_vl_rfs.sv File Reference

Go to the source code of this file.

Functions
DowngradeIPIdentifiedWarnings module	axi_vip_v1_1_8_top (parameter C_AXI_PROTOCOL=0, parameter C_AXI_INTERFACE_MODE=1, parameter integer C_AXI_ADDR_WIDTH=32, parameter integer C_AXI_WDATA_WIDTH=32, parameter integer C_AXI_RDATA_WIDTH=32, parameter integer C_AXI_WID_WIDTH=0, parameter integer C_AXI_RID_WIDTH=0, parameter integer C_AXI_AWUSER_WIDTH=0, parameter integer C_AXI_ARUSER_WIDTH=0, parameter integer C_AXI_WUSER_WIDTH=0, parameter integer C_AXI_RUSER_WIDTH=0, parameter integer C_AXI_BUSER_WIDTH=0, parameter integer C_AXI_SUPPORTS_NARROW=1, parameter integer C_AXI_HAS_BURST=1, parameter integer C_AXI_HAS_LOCK=1, parameter integer C_AXI_HAS_CACHE=1, parameter integer C_AXI_HAS_REGION=1, parameter integer C_AXI_HAS_PROT=1, parameter integer C_AXI_HAS_QOS=1, parameter integer C_AXI_HAS_WSTRB=1, parameter integer C_AXI_HAS_BRESP=1, parameter integer C_AXI_HAS_RRESP=1, parameter integer C_AXI_HAS_ARESETN=1)(input wire aclk
axi_vip_if< .C_AXI_PROTOCOL(C_AXI_PROTOCOL),.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH),.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH),.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH),.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH),.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),.C_AXI_HAS_BURST(C_AXI_HAS_BURST),.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),.C_AXI_HAS_REGION(C_AXI_HAS_REGION),.C_AXI_HAS_PROT(C_AXI_HAS_PROT),.C_AXI_HAS_QOS(C_AXI_HAS_QOS),.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN) >	IF (.ACLK(aclk),.ARESET_N(aresetn),.ACLKEN(aclken))

Variables
DowngradeIPIdentifiedWarnings module input wire	aclken
DowngradeIPIdentifiedWarnings module input wire input wire	aresetn
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 >	s_axi_awid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 >	s_axi_awaddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 >	s_axi_awlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 >	s_axi_awsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 >	s_axi_awburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 >	s_axi_awlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 >	s_axi_awcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 >	s_axi_awprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 >	s_axi_awregion
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 >	s_axi_awqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 >	s_axi_awuser
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire	s_axi_awvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire	s_axi_awready = slave_mode? IF.AWREADY : {0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 >	s_axi_wid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 >	s_axi_wdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 >	s_axi_wstrb
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire	s_axi_wlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 >	s_axi_wuser
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire	s_axi_wvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire	s_axi_wready = slave_mode? IF.WREADY : {0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 >	s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 >	s_axi_bresp = slave_mode? IF.BRESP : {2{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 >	s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire	s_axi_bvalid = slave_mode? IF.BVALID : {1{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire	s_axi_bready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 >	s_axi_arid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 >	s_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 >	s_axi_arlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 >	s_axi_arsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 >	s_axi_arburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 >	s_axi_arlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 >	s_axi_arcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 >	s_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 >	s_axi_arregion
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 >	s_axi_arqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 >	s_axi_aruser
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire	s_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire	s_axi_arready = slave_mode? IF.ARREADY : {0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 >	s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 >	s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 >	s_axi_rresp = slave_mode? IF.RRESP : {2{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire	s_axi_rlast = slave_mode? IF.RLAST : {{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 >	s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire	s_axi_rvalid = slave_mode? IF.RVALID : {{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire	s_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 >	m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 >	m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 >	m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 >	m_axi_awsize = master_mode? IF.AWSIZE : {3{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 >	m_axi_awburst = master_mode? IF.AWBURST : {2{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 >	m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 >	m_axi_awcache = master_mode? IF.AWCACHE : {4{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 >	m_axi_awprot = master_mode? IF.AWPROT : {3{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 >	m_axi_awregion = master_mode? IF.AWREGION : {4{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 >	m_axi_awqos = master_mode? IF.AWQOS : {4{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 >	m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire	m_axi_awvalid = master_mode? IF.AWVALID :{0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire	m_axi_awready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 >	m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 >	m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 >	m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire	m_axi_wlast = master_mode? IF.WLAST : {0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 >	m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire	m_axi_wvalid = master_mode? IF.WVALID : {0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire	m_axi_wready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 >	m_axi_bid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 >	m_axi_bresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 >	m_axi_buser
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire	m_axi_bvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire	m_axi_bready = master_mode? IF.BREADY : 0b0
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 >	m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 >	m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 >	m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 >	m_axi_arsize = master_mode? IF.ARSIZE : {3{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 >	m_axi_arburst = master_mode? IF.ARBURST : {2{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 >	m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 >	m_axi_arcache = master_mode?IF.ARCACHE : {4{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 >	m_axi_arprot = master_mode? IF.ARPROT : {3{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 >	m_axi_arregion = master_mode? IF.ARREGION : {4{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 >	m_axi_arqos = master_mode? IF.ARQOS : {4{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 >	m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{0b0}}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire	m_axi_arvalid = master_mode? IF.ARVALID :{0b0}
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire	m_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 >	m_axi_rid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 >	m_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 >	m_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire	m_axi_rlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 >	m_axi_ruser
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire	m_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire output wire	m_axi_rready
logic	runtime_slave =0
wire	run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0
wire	run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0)
wire	run_passth_mode = (runtime_slave ==0 && runtime_master ==0)
wire	compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode
wire	compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode
wire	master_mode = compile_master_mode || run_master_mode
wire	slave_mode = compile_slave_mode || run_slave_mode
assign IF	AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0bz}}
assign IF	AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{0bz}}
assign IF	AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){0bz}}
assign IF	AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{0bz}}
assign IF	AWBURST = slave_mode? s_axi_awburst : {2{0bz}}
assign IF	AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0bz}}
assign IF	AWCACHE = slave_mode? s_axi_awcache : {4{0bz}}
assign IF	AWPROT = slave_mode? s_axi_awprot : {3{0bz}}
assign IF	AWREGION = slave_mode? s_axi_awregion : {4{0bz}}
assign IF	AWQOS = slave_mode? s_axi_awqos : {4{0bz}}
assign IF	AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{0bz}}
assign IF	AWVALID = slave_mode? s_axi_awvalid : {0bz}
assign IF	WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0bz}}
assign IF	WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{0bz}}
assign IF	WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){0bz}}
assign IF	WLAST = slave_mode? s_axi_wlast: {0bz}
assign IF	WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{0bz}}
assign IF	WVALID = slave_mode? s_axi_wvalid : {0bz}
assign IF	BREADY = slave_mode? s_axi_bready :{1{0bz}}
assign IF	ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0bz}}
assign IF	ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{0bz}}
assign IF	ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){0bz}}
assign IF	ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{0bz}}
assign IF	ARBURST = slave_mode? s_axi_arburst : {2{0bz}}
assign IF	ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0bz}}
assign IF	ARCACHE = slave_mode? s_axi_arcache : {4{0bz}}
assign IF	ARPROT = slave_mode? s_axi_arprot : {3{0bz}}
assign IF	ARREGION = slave_mode? s_axi_arregion :{4{0bz}}
assign IF	ARQOS = slave_mode? s_axi_arqos : {4{0bz}}
assign IF	ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{0bz}}
assign IF	ARVALID = slave_mode? s_axi_arvalid : {0bz}
assign IF	RREADY = slave_mode? s_axi_rready:{{0bz}}
assign IF	AWREADY = master_mode? m_axi_awready :{0bz}
assign IF	WREADY = master_mode? m_axi_wready : {0bz}
assign IF	BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0bz}}
assign IF	BRESP = master_mode? m_axi_bresp : {2{0bz}}
assign IF	BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{0bz}}
assign IF	BVALID = master_mode? m_axi_bvalid : 0bz
assign IF	ARREADY = master_mode? m_axi_arready : {1{0bz}}
assign IF	RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0bz}}
assign IF	RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{0bz}}
assign IF	RRESP = master_mode? m_axi_rresp : {2{0bz}}
assign IF	RLAST = master_mode? m_axi_rlast : {1{0bz}}
assign IF	RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{0bz}}
assign IF	RVALID = master_mode? m_axi_rvalid : {1{0bz}}

Function Documentation

IF()

axi_vip_if< .C_AXI_PROTOCOL(C_AXI_PROTOCOL), .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ), .C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ), .C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ), .C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ), .C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ), .C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ), .C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ), .C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ), .C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ), .C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ), .C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW), .C_AXI_HAS_BURST(C_AXI_HAS_BURST), .C_AXI_HAS_LOCK(C_AXI_HAS_LOCK), .C_AXI_HAS_CACHE(C_AXI_HAS_CACHE), .C_AXI_HAS_REGION(C_AXI_HAS_REGION), .C_AXI_HAS_PROT(C_AXI_HAS_PROT), .C_AXI_HAS_QOS(C_AXI_HAS_QOS), .C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB), .C_AXI_HAS_BRESP(C_AXI_HAS_BRESP), .C_AXI_HAS_RRESP(C_AXI_HAS_RRESP), .C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN) > IF	(	.	ACLKaclk,
		.	ARESET_Naresetn,
		.	ACLKENaclken
	)

Variable Documentation

aclken

DowngradeIPIdentifiedWarnings module input wire aclken

Definition at line 93 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

ARADDR

assign IF ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{0bz}}

Definition at line 285 of file axi_vip_v1_1_vl_rfs.sv.

ARBURST

assign IF ARBURST = slave_mode? s_axi_arburst : {2{0bz}}

Definition at line 288 of file axi_vip_v1_1_vl_rfs.sv.

ARCACHE

assign IF ARCACHE = slave_mode? s_axi_arcache : {4{0bz}}

Definition at line 290 of file axi_vip_v1_1_vl_rfs.sv.

aresetn

DowngradeIPIdentifiedWarnings module input wire input wire aresetn

Definition at line 94 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

ARID

assign IF ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0bz}}

Definition at line 284 of file axi_vip_v1_1_vl_rfs.sv.

ARLEN

assign IF ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){0bz}}

Definition at line 286 of file axi_vip_v1_1_vl_rfs.sv.

ARLOCK

assign IF ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0bz}}

Definition at line 289 of file axi_vip_v1_1_vl_rfs.sv.

ARPROT

assign IF ARPROT = slave_mode? s_axi_arprot : {3{0bz}}

Definition at line 291 of file axi_vip_v1_1_vl_rfs.sv.

ARQOS

assign IF ARQOS = slave_mode? s_axi_arqos : {4{0bz}}

Definition at line 293 of file axi_vip_v1_1_vl_rfs.sv.

ARREADY

assign IF ARREADY = master_mode? m_axi_arready : {1{0bz}}

Definition at line 351 of file axi_vip_v1_1_vl_rfs.sv.

ARREGION

assign IF ARREGION = slave_mode? s_axi_arregion :{4{0bz}}

Definition at line 292 of file axi_vip_v1_1_vl_rfs.sv.

ARSIZE

assign IF ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{0bz}}

Definition at line 287 of file axi_vip_v1_1_vl_rfs.sv.

ARUSER

assign IF ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{0bz}}

Definition at line 294 of file axi_vip_v1_1_vl_rfs.sv.

ARVALID

assign IF ARVALID = slave_mode? s_axi_arvalid : {0bz}

Definition at line 295 of file axi_vip_v1_1_vl_rfs.sv.

AWADDR

assign IF AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{0bz}}

Definition at line 254 of file axi_vip_v1_1_vl_rfs.sv.

AWBURST

assign IF AWBURST = slave_mode? s_axi_awburst : {2{0bz}}

Definition at line 257 of file axi_vip_v1_1_vl_rfs.sv.

AWCACHE

assign IF AWCACHE = slave_mode? s_axi_awcache : {4{0bz}}

Definition at line 259 of file axi_vip_v1_1_vl_rfs.sv.

AWID

assign IF AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0bz}}

Definition at line 253 of file axi_vip_v1_1_vl_rfs.sv.

AWLEN

assign IF AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){0bz}}

Definition at line 255 of file axi_vip_v1_1_vl_rfs.sv.

AWLOCK

assign IF AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0bz}}

Definition at line 258 of file axi_vip_v1_1_vl_rfs.sv.

AWPROT

assign IF AWPROT = slave_mode? s_axi_awprot : {3{0bz}}

Definition at line 260 of file axi_vip_v1_1_vl_rfs.sv.

AWQOS

assign IF AWQOS = slave_mode? s_axi_awqos : {4{0bz}}

Definition at line 262 of file axi_vip_v1_1_vl_rfs.sv.

AWREADY

assign IF AWREADY = master_mode? m_axi_awready :{0bz}

Definition at line 320 of file axi_vip_v1_1_vl_rfs.sv.

AWREGION

assign IF AWREGION = slave_mode? s_axi_awregion : {4{0bz}}

Definition at line 261 of file axi_vip_v1_1_vl_rfs.sv.

AWSIZE

assign IF AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{0bz}}

Definition at line 256 of file axi_vip_v1_1_vl_rfs.sv.

AWUSER

assign IF AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{0bz}}

Definition at line 263 of file axi_vip_v1_1_vl_rfs.sv.

AWVALID

assign IF AWVALID = slave_mode? s_axi_awvalid : {0bz}

Definition at line 264 of file axi_vip_v1_1_vl_rfs.sv.

BID

assign IF BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0bz}}

Definition at line 332 of file axi_vip_v1_1_vl_rfs.sv.

BREADY

assign IF BREADY = slave_mode? s_axi_bready :{1{0bz}}

Definition at line 281 of file axi_vip_v1_1_vl_rfs.sv.

BRESP

assign IF BRESP = master_mode? m_axi_bresp : {2{0bz}}

Definition at line 333 of file axi_vip_v1_1_vl_rfs.sv.

BUSER

assign IF BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{0bz}}

Definition at line 334 of file axi_vip_v1_1_vl_rfs.sv.

BVALID

assign IF BVALID = master_mode? m_axi_bvalid : 0bz

Definition at line 335 of file axi_vip_v1_1_vl_rfs.sv.

compile_master_mode

assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode

Definition at line 237 of file axi_vip_v1_1_vl_rfs.sv.

compile_slave_mode

assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode

Definition at line 238 of file axi_vip_v1_1_vl_rfs.sv.

m_axi_araddr

assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{0b0}}

Definition at line 184 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arburst

assign m_axi_arburst = master_mode? IF.ARBURST : {2{0b0}}

Definition at line 187 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arcache

assign m_axi_arcache = master_mode?IF.ARCACHE : {4{0b0}}

Definition at line 189 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arid

assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0b0}}

Definition at line 183 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arlen

assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){0b0}}

Definition at line 185 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arlock

assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0b0}}

Definition at line 188 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arprot

assign m_axi_arprot = master_mode? IF.ARPROT : {3{0b0}}

Definition at line 190 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arqos

assign m_axi_arqos = master_mode? IF.ARQOS : {4{0b0}}

Definition at line 192 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arready

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire m_axi_arready

Definition at line 195 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arregion

assign m_axi_arregion = master_mode? IF.ARREGION : {4{0b0}}

Definition at line 191 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arsize

assign m_axi_arsize = master_mode? IF.ARSIZE : {3{0b0}}

Definition at line 186 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_aruser

assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{0b0}}

Definition at line 193 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_arvalid

assign m_axi_arvalid = master_mode? IF.ARVALID :{0b0}

Definition at line 194 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awaddr

assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{0b0}}

Definition at line 153 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awburst

assign m_axi_awburst = master_mode? IF.AWBURST : {2{0b0}}

Definition at line 156 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awcache

assign m_axi_awcache = master_mode? IF.AWCACHE : {4{0b0}}

Definition at line 158 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awid

assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0b0}}

Definition at line 152 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awlen

assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){0b0}}

Definition at line 154 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awlock

assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){0b0}}

Definition at line 157 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awprot

assign m_axi_awprot = master_mode? IF.AWPROT : {3{0b0}}

Definition at line 159 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awqos

assign m_axi_awqos = master_mode? IF.AWQOS : {4{0b0}}

Definition at line 161 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awready

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire m_axi_awready

Definition at line 164 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awregion

assign m_axi_awregion = master_mode? IF.AWREGION : {4{0b0}}

Definition at line 160 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awsize

assign m_axi_awsize = master_mode? IF.AWSIZE : {3{0b0}}

Definition at line 155 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awuser

assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{0b0}}

Definition at line 162 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_awvalid

assign m_axi_awvalid = master_mode? IF.AWVALID :{0b0}

Definition at line 163 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_bid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> m_axi_bid

Definition at line 176 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_bready

assign m_axi_bready = master_mode? IF.BREADY : 0b0

Definition at line 180 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_bresp

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> m_axi_bresp

Definition at line 177 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_buser

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> m_axi_buser

Definition at line 178 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_bvalid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire m_axi_bvalid

Definition at line 179 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_rdata

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_RDATA_WIDTH-1:0> m_axi_rdata

Definition at line 199 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_rid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> m_axi_rid

Definition at line 198 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_rlast

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_RDATA_WIDTH-1:0> input wire<2-1:0> input wire m_axi_rlast

Definition at line 201 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_rready

assign m_axi_rready

Initial value:

{
   
  
 
  
 
  logic runtime_master =0

Definition at line 205 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_rresp

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_RDATA_WIDTH-1:0> input wire<2-1:0> m_axi_rresp

Definition at line 200 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_ruser

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_RDATA_WIDTH-1:0> input wire<2-1:0> input wire input wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> m_axi_ruser

Definition at line 202 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_rvalid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<2-1:0> input wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire< C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_RDATA_WIDTH-1:0> input wire<2-1:0> input wire input wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> input wire m_axi_rvalid

Definition at line 203 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wdata

assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{0b0}}

Definition at line 168 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wid

assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0b0}}

Definition at line 167 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wlast

assign m_axi_wlast = master_mode? IF.WLAST : {0b0}

Definition at line 170 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wready

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_ADDR_WIDTH-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> output wire<3-1:0> output wire<2-1:0> output wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> output wire<4-1:0> output wire<3-1:0> output wire<4-1:0> output wire<4-1:0> output wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> output wire input wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH-1:0> output wire<C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0> output wire output wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> output wire input wire m_axi_wready

Definition at line 173 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wstrb

assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){0b0}}

Definition at line 169 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wuser

assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{0b0}}

Definition at line 171 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

m_axi_wvalid

assign m_axi_wvalid = master_mode? IF.WVALID : {0b0}

Definition at line 172 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

master_mode

assign master_mode = compile_master_mode || run_master_mode

Definition at line 239 of file axi_vip_v1_1_vl_rfs.sv.

RDATA

assign IF RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{0bz}}

Definition at line 355 of file axi_vip_v1_1_vl_rfs.sv.

RID

assign IF RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0bz}}

Definition at line 354 of file axi_vip_v1_1_vl_rfs.sv.

RLAST

assign IF RLAST = master_mode? m_axi_rlast : {1{0bz}}

Definition at line 357 of file axi_vip_v1_1_vl_rfs.sv.

RREADY

assign IF RREADY = slave_mode? s_axi_rready:{{0bz}}

Definition at line 305 of file axi_vip_v1_1_vl_rfs.sv.

RRESP

assign IF RRESP = master_mode? m_axi_rresp : {2{0bz}}

Definition at line 356 of file axi_vip_v1_1_vl_rfs.sv.

run_master_mode

assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0)

Definition at line 235 of file axi_vip_v1_1_vl_rfs.sv.

run_passth_mode

assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0)

Definition at line 236 of file axi_vip_v1_1_vl_rfs.sv.

run_slave_mode

assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0

Definition at line 234 of file axi_vip_v1_1_vl_rfs.sv.

runtime_slave

logic runtime_slave =0

Definition at line 232 of file axi_vip_v1_1_vl_rfs.sv.

RUSER

assign IF RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{0bz}}

Definition at line 358 of file axi_vip_v1_1_vl_rfs.sv.

RVALID

assign IF RVALID = master_mode? m_axi_rvalid : {1{0bz}}

Definition at line 359 of file axi_vip_v1_1_vl_rfs.sv.

s_axi_araddr

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> s_axi_araddr

Definition at line 129 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arburst

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> s_axi_arburst

Definition at line 132 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arcache

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> s_axi_arcache

Definition at line 134 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> s_axi_arid

Definition at line 128 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arlen

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> s_axi_arlen

Definition at line 130 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arlock

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> s_axi_arlock

Definition at line 133 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arprot

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> s_axi_arprot

Definition at line 135 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arqos

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> s_axi_arqos

Definition at line 137 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arready

assign s_axi_arready = slave_mode? IF.ARREADY : {0b0}

Definition at line 140 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arregion

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> s_axi_arregion

Definition at line 136 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arsize

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> s_axi_arsize

Definition at line 131 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_aruser

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> s_axi_aruser

Definition at line 138 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_arvalid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire s_axi_arvalid

Definition at line 139 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awaddr

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> s_axi_awaddr

Definition at line 98 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awburst

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> s_axi_awburst

Definition at line 101 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awcache

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> s_axi_awcache

Definition at line 103 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> s_axi_awid

Definition at line 97 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awlen

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> s_axi_awlen

Definition at line 99 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awlock

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> s_axi_awlock

Definition at line 102 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awprot

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> s_axi_awprot

Definition at line 104 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awqos

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> s_axi_awqos

Definition at line 106 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awready

assign s_axi_awready = slave_mode? IF.AWREADY : {0b0}

Definition at line 109 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awregion

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> s_axi_awregion

Definition at line 105 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awsize

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> s_axi_awsize

Definition at line 100 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awuser

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> s_axi_awuser

Definition at line 107 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_awvalid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire s_axi_awvalid

Definition at line 108 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_bid

assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0b0}}

Definition at line 121 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_bready

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire s_axi_bready

Definition at line 125 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_bresp

assign s_axi_bresp = slave_mode? IF.BRESP : {2{0b0}}

Definition at line 122 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_buser

assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{0b0}}

Definition at line 123 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_bvalid

assign s_axi_bvalid = slave_mode? IF.BVALID : {1{0b0}}

Definition at line 124 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_rdata

assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{0b0}}

Definition at line 144 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_rid

assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{0b0}}

Definition at line 143 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_rlast

assign s_axi_rlast = slave_mode? IF.RLAST : {{0b0}}

Definition at line 146 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_rready

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> output wire<2-1:0> output wire<C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0> output wire input wire input wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0> input wire output wire output wire<C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0> output wire<C_AXI_RDATA_WIDTH-1:0> output wire<2-1:0> output wire output wire<C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0> output wire input wire s_axi_rready

Definition at line 149 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_rresp

assign s_axi_rresp = slave_mode? IF.RRESP : {2{0b0}}

Definition at line 145 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_ruser

assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{0b0}}

Definition at line 147 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_rvalid

assign s_axi_rvalid = slave_mode? IF.RVALID : {{0b0}}

Definition at line 148 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wdata

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> s_axi_wdata

Definition at line 113 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> s_axi_wid

Definition at line 112 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wlast

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire s_axi_wlast

Definition at line 115 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wready

assign s_axi_wready = slave_mode? IF.WREADY : {0b0}

Definition at line 118 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wstrb

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> s_axi_wstrb

Definition at line 114 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wuser

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> s_axi_wuser

Definition at line 116 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

s_axi_wvalid

DowngradeIPIdentifiedWarnings module input wire input wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_ADDR_WIDTH-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0> input wire<3-1:0> input wire<2-1:0> input wire<((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0> input wire<4-1:0> input wire<3-1:0> input wire<4-1:0> input wire<4-1:0> input wire<C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0> input wire output wire input wire<C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH-1:0> input wire<C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0> input wire input wire<C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0> input wire s_axi_wvalid

Definition at line 117 of file axi_vip_v1_1_vl_rfs.sv.

Referenced by processing_system7_vip_v1_0_10_afi_slave(), processing_system7_vip_v1_0_10_axi_master(), processing_system7_vip_v1_0_10_axi_slave(), and processing_system7_vip_v1_0_10_axi_slave_acp().

slave_mode

assign slave_mode = compile_slave_mode || run_slave_mode

Definition at line 240 of file axi_vip_v1_1_vl_rfs.sv.

WDATA

assign IF WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{0bz}}

Definition at line 269 of file axi_vip_v1_1_vl_rfs.sv.

WID

assign IF WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{0bz}}

Definition at line 268 of file axi_vip_v1_1_vl_rfs.sv.

WLAST

assign IF WLAST = slave_mode? s_axi_wlast: {0bz}

Definition at line 271 of file axi_vip_v1_1_vl_rfs.sv.

WREADY

assign IF WREADY = master_mode? m_axi_wready : {0bz}

Definition at line 329 of file axi_vip_v1_1_vl_rfs.sv.

WSTRB

assign IF WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){0bz}}

Definition at line 270 of file axi_vip_v1_1_vl_rfs.sv.

WUSER

assign IF WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{0bz}}

Definition at line 272 of file axi_vip_v1_1_vl_rfs.sv.

WVALID

assign IF WVALID = slave_mode? s_axi_wvalid : {0bz}

Definition at line 273 of file axi_vip_v1_1_vl_rfs.sv.