SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_xbar_0_sc.h
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1 #ifndef IP_DESIGN_1_XBAR_0_SC_H_
2 #define IP_DESIGN_1_XBAR_0_SC_H_
3 
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51 
52 
53 #ifndef XTLM
54 #include "xtlm.h"
55 #endif
56 #ifndef SYSTEMC_INCLUDED
57 #include <systemc>
58 #endif
59 
60 #if defined(_MSC_VER)
61 #define DllExport __declspec(dllexport)
62 #elif defined(__GNUC__)
63 #define DllExport __attribute__ ((visibility("default")))
64 #else
65 #define DllExport
66 #endif
67 
68 class axi_crossbar;
69 
70 class DllExport design_1_xbar_0_sc : public sc_core::sc_module
71 {
72 public:
73 
74  design_1_xbar_0_sc(const sc_core::sc_module_name& nm);
75  virtual ~design_1_xbar_0_sc();
76 
77  // module socket-to-socket AXI TLM interfaces
78 
79  xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
80  xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
81  xtlm::xtlm_aximm_initiator_socket* initiator_0_rd_socket;
82  xtlm::xtlm_aximm_initiator_socket* initiator_0_wr_socket;
83  xtlm::xtlm_aximm_initiator_socket* initiator_1_rd_socket;
84  xtlm::xtlm_aximm_initiator_socket* initiator_1_wr_socket;
85  xtlm::xtlm_aximm_initiator_socket* initiator_2_rd_socket;
86  xtlm::xtlm_aximm_initiator_socket* initiator_2_wr_socket;
87 
88  // module socket-to-socket TLM interfaces
89 
90 
91 protected:
92 
94 
95 private:
96 
98  const design_1_xbar_0_sc& operator=(const design_1_xbar_0_sc&);
99 
100 };
101 
102 #endif // IP_DESIGN_1_XBAR_0_SC_H_
DllExport
#define DllExport
Definition: design_1_xbar_0_sc.h:65
design_1_xbar_0_sc::initiator_2_rd_socket
xtlm::xtlm_aximm_initiator_socket * initiator_2_rd_socket
Definition: design_1_xbar_0_sc.h:85
design_1_xbar_0_sc
Definition: design_1_xbar_0_sc.h:70
design_1_xbar_0_sc::initiator_0_rd_socket
xtlm::xtlm_aximm_initiator_socket * initiator_0_rd_socket
Definition: design_1_xbar_0_sc.h:81
design_1_xbar_0_sc::target_0_rd_socket
xtlm::xtlm_aximm_target_socket * target_0_rd_socket
Definition: design_1_xbar_0_sc.h:79
axi_crossbar
Definition: axi_crossbar.h:8
design_1_xbar_0_sc::initiator_1_wr_socket
xtlm::xtlm_aximm_initiator_socket * initiator_1_wr_socket
Definition: design_1_xbar_0_sc.h:84
design_1_xbar_0_sc::initiator_1_rd_socket
xtlm::xtlm_aximm_initiator_socket * initiator_1_rd_socket
Definition: design_1_xbar_0_sc.h:83
design_1_xbar_0_sc::initiator_0_wr_socket
xtlm::xtlm_aximm_initiator_socket * initiator_0_wr_socket
Definition: design_1_xbar_0_sc.h:82
design_1_xbar_0_sc::mp_impl
axi_crossbar * mp_impl
Definition: design_1_xbar_0_sc.h:93
design_1_xbar_0_sc::target_0_wr_socket
xtlm::xtlm_aximm_target_socket * target_0_wr_socket
Definition: design_1_xbar_0_sc.h:80
design_1_xbar_0_sc::initiator_2_wr_socket
xtlm::xtlm_aximm_initiator_socket * initiator_2_wr_socket
Definition: design_1_xbar_0_sc.h:86