SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_auto_pc_1.cpp
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48 
49 
50 #include "design_1_auto_pc_1_sc.h"
51 
52 #include "design_1_auto_pc_1.h"
53 
54 #include "axi_protocol_converter.h"
55 
56 #include <map>
57 #include <string>
58 
59 
60 
61 
62 
63 #ifdef XILINX_SIMULATOR
64 design_1_auto_pc_1::design_1_auto_pc_1(const sc_core::sc_module_name& nm) : design_1_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wid("s_axi_wid"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
65 {
66 
67  // initialize pins
68  mp_impl->aclk(aclk);
69  mp_impl->aresetn(aresetn);
70 
71  // initialize transactors
72  mp_S_AXI_transactor = NULL;
73  mp_s_axi_awlen_converter = NULL;
74  mp_s_axi_awlock_converter = NULL;
75  mp_s_axi_arlen_converter = NULL;
76  mp_s_axi_arlock_converter = NULL;
77  mp_M_AXI_transactor = NULL;
78 
79  // initialize socket stubs
80 
81 }
82 
83 void design_1_auto_pc_1::before_end_of_elaboration()
84 {
85  // configure 'S_AXI' transactor
86 
87  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "S_AXI_TLM_MODE") != 1)
88  {
89  // Instantiate Socket Stubs
90 
91  // 'S_AXI' transactor parameters
92  xsc::common_cpp::properties S_AXI_transactor_param_props;
93  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
94  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
95  S_AXI_transactor_param_props.addLong("ID_WIDTH", "12");
96  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
97  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
98  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
99  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
100  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
101  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
102  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
103  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
104  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
105  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
106  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
107  S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
108  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
109  S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
110  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
111  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
112  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
113  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
114  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
115  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
116  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
117  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
118  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
119  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
120  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
121  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
122  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
123  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
124  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
125 
126  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
127 
128  // S_AXI' transactor ports
129 
130  mp_S_AXI_transactor->AWID(s_axi_awid);
131  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
132  mp_s_axi_awlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_awlen_converter");
133  mp_s_axi_awlen_converter->vector_in(s_axi_awlen);
134  mp_s_axi_awlen_converter->vector_out(m_s_axi_awlen_converter_signal);
135  mp_S_AXI_transactor->AWLEN(m_s_axi_awlen_converter_signal);
136  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
137  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
138  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_awlock_converter");
139  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
140  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
141  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
142  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
143  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
144  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
145  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
146  mp_S_AXI_transactor->AWREADY(s_axi_awready);
147  mp_S_AXI_transactor->WDATA(s_axi_wdata);
148  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
149  mp_S_AXI_transactor->WLAST(s_axi_wlast);
150  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
151  mp_S_AXI_transactor->WREADY(s_axi_wready);
152  mp_S_AXI_transactor->BID(s_axi_bid);
153  mp_S_AXI_transactor->BRESP(s_axi_bresp);
154  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
155  mp_S_AXI_transactor->BREADY(s_axi_bready);
156  mp_S_AXI_transactor->ARID(s_axi_arid);
157  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
158  mp_s_axi_arlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_arlen_converter");
159  mp_s_axi_arlen_converter->vector_in(s_axi_arlen);
160  mp_s_axi_arlen_converter->vector_out(m_s_axi_arlen_converter_signal);
161  mp_S_AXI_transactor->ARLEN(m_s_axi_arlen_converter_signal);
162  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
163  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
164  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_arlock_converter");
165  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
166  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
167  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
168  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
169  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
170  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
171  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
172  mp_S_AXI_transactor->ARREADY(s_axi_arready);
173  mp_S_AXI_transactor->RID(s_axi_rid);
174  mp_S_AXI_transactor->RDATA(s_axi_rdata);
175  mp_S_AXI_transactor->RRESP(s_axi_rresp);
176  mp_S_AXI_transactor->RLAST(s_axi_rlast);
177  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
178  mp_S_AXI_transactor->RREADY(s_axi_rready);
179  mp_S_AXI_transactor->CLK(aclk);
180  mp_S_AXI_transactor->RST(aresetn);
181 
182  // S_AXI' transactor sockets
183 
184  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
185  mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
186  }
187  else
188  {
189  }
190 
191  // configure 'M_AXI' transactor
192 
193  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "M_AXI_TLM_MODE") != 1)
194  {
195  // Instantiate Socket Stubs
196 
197  // 'M_AXI' transactor parameters
198  xsc::common_cpp::properties M_AXI_transactor_param_props;
199  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
200  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
201  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
202  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
203  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
204  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
205  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
206  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
207  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
208  M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
209  M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
210  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
211  M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
212  M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
213  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
214  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
215  M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
216  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
217  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
218  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
219  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
220  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
221  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
222  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
223  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
224  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
225  M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
226  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
227  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
228  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
229  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
230  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
231 
232  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
233 
234  // M_AXI' transactor ports
235 
236  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
237  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
238  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
239  mp_M_AXI_transactor->AWREADY(m_axi_awready);
240  mp_M_AXI_transactor->WDATA(m_axi_wdata);
241  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
242  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
243  mp_M_AXI_transactor->WREADY(m_axi_wready);
244  mp_M_AXI_transactor->BRESP(m_axi_bresp);
245  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
246  mp_M_AXI_transactor->BREADY(m_axi_bready);
247  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
248  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
249  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
250  mp_M_AXI_transactor->ARREADY(m_axi_arready);
251  mp_M_AXI_transactor->RDATA(m_axi_rdata);
252  mp_M_AXI_transactor->RRESP(m_axi_rresp);
253  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
254  mp_M_AXI_transactor->RREADY(m_axi_rready);
255  mp_M_AXI_transactor->CLK(aclk);
256  mp_M_AXI_transactor->RST(aresetn);
257 
258  // M_AXI' transactor sockets
259 
260  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
261  mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
262  }
263  else
264  {
265  }
266 
267 }
268 
269 #endif // XILINX_SIMULATOR
270 
271 
272 
273 
274 #ifdef XM_SYSTEMC
275 design_1_auto_pc_1::design_1_auto_pc_1(const sc_core::sc_module_name& nm) : design_1_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wid("s_axi_wid"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
276 {
277 
278  // initialize pins
279  mp_impl->aclk(aclk);
280  mp_impl->aresetn(aresetn);
281 
282  // initialize transactors
283  mp_S_AXI_transactor = NULL;
284  mp_s_axi_awlen_converter = NULL;
285  mp_s_axi_awlock_converter = NULL;
286  mp_s_axi_arlen_converter = NULL;
287  mp_s_axi_arlock_converter = NULL;
288  mp_M_AXI_transactor = NULL;
289 
290  // initialize socket stubs
291 
292 }
293 
294 void design_1_auto_pc_1::before_end_of_elaboration()
295 {
296  // configure 'S_AXI' transactor
297 
298  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "S_AXI_TLM_MODE") != 1)
299  {
300  // Instantiate Socket Stubs
301 
302  // 'S_AXI' transactor parameters
303  xsc::common_cpp::properties S_AXI_transactor_param_props;
304  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
305  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
306  S_AXI_transactor_param_props.addLong("ID_WIDTH", "12");
307  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
308  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
309  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
310  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
311  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
312  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
313  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
314  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
315  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
316  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
317  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
318  S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
319  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
320  S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
321  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
322  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
323  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
324  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
325  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
326  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
327  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
328  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
329  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
330  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
331  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
332  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
333  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
334  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
335  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
336 
337  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
338 
339  // S_AXI' transactor ports
340 
341  mp_S_AXI_transactor->AWID(s_axi_awid);
342  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
343  mp_s_axi_awlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_awlen_converter");
344  mp_s_axi_awlen_converter->vector_in(s_axi_awlen);
345  mp_s_axi_awlen_converter->vector_out(m_s_axi_awlen_converter_signal);
346  mp_S_AXI_transactor->AWLEN(m_s_axi_awlen_converter_signal);
347  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
348  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
349  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_awlock_converter");
350  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
351  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
352  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
353  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
354  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
355  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
356  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
357  mp_S_AXI_transactor->AWREADY(s_axi_awready);
358  mp_S_AXI_transactor->WDATA(s_axi_wdata);
359  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
360  mp_S_AXI_transactor->WLAST(s_axi_wlast);
361  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
362  mp_S_AXI_transactor->WREADY(s_axi_wready);
363  mp_S_AXI_transactor->BID(s_axi_bid);
364  mp_S_AXI_transactor->BRESP(s_axi_bresp);
365  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
366  mp_S_AXI_transactor->BREADY(s_axi_bready);
367  mp_S_AXI_transactor->ARID(s_axi_arid);
368  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
369  mp_s_axi_arlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_arlen_converter");
370  mp_s_axi_arlen_converter->vector_in(s_axi_arlen);
371  mp_s_axi_arlen_converter->vector_out(m_s_axi_arlen_converter_signal);
372  mp_S_AXI_transactor->ARLEN(m_s_axi_arlen_converter_signal);
373  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
374  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
375  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_arlock_converter");
376  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
377  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
378  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
379  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
380  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
381  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
382  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
383  mp_S_AXI_transactor->ARREADY(s_axi_arready);
384  mp_S_AXI_transactor->RID(s_axi_rid);
385  mp_S_AXI_transactor->RDATA(s_axi_rdata);
386  mp_S_AXI_transactor->RRESP(s_axi_rresp);
387  mp_S_AXI_transactor->RLAST(s_axi_rlast);
388  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
389  mp_S_AXI_transactor->RREADY(s_axi_rready);
390  mp_S_AXI_transactor->CLK(aclk);
391  mp_S_AXI_transactor->RST(aresetn);
392 
393  // S_AXI' transactor sockets
394 
395  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
396  mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
397  }
398  else
399  {
400  }
401 
402  // configure 'M_AXI' transactor
403 
404  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "M_AXI_TLM_MODE") != 1)
405  {
406  // Instantiate Socket Stubs
407 
408  // 'M_AXI' transactor parameters
409  xsc::common_cpp::properties M_AXI_transactor_param_props;
410  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
411  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
412  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
413  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
414  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
415  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
416  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
417  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
418  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
419  M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
420  M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
421  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
422  M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
423  M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
424  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
425  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
426  M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
427  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
428  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
429  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
430  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
431  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
432  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
433  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
434  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
435  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
436  M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
437  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
438  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
439  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
440  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
441  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
442 
443  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
444 
445  // M_AXI' transactor ports
446 
447  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
448  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
449  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
450  mp_M_AXI_transactor->AWREADY(m_axi_awready);
451  mp_M_AXI_transactor->WDATA(m_axi_wdata);
452  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
453  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
454  mp_M_AXI_transactor->WREADY(m_axi_wready);
455  mp_M_AXI_transactor->BRESP(m_axi_bresp);
456  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
457  mp_M_AXI_transactor->BREADY(m_axi_bready);
458  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
459  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
460  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
461  mp_M_AXI_transactor->ARREADY(m_axi_arready);
462  mp_M_AXI_transactor->RDATA(m_axi_rdata);
463  mp_M_AXI_transactor->RRESP(m_axi_rresp);
464  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
465  mp_M_AXI_transactor->RREADY(m_axi_rready);
466  mp_M_AXI_transactor->CLK(aclk);
467  mp_M_AXI_transactor->RST(aresetn);
468 
469  // M_AXI' transactor sockets
470 
471  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
472  mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
473  }
474  else
475  {
476  }
477 
478 }
479 
480 #endif // XM_SYSTEMC
481 
482 
483 
484 
485 #ifdef RIVIERA
486 design_1_auto_pc_1::design_1_auto_pc_1(const sc_core::sc_module_name& nm) : design_1_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wid("s_axi_wid"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
487 {
488 
489  // initialize pins
490  mp_impl->aclk(aclk);
491  mp_impl->aresetn(aresetn);
492 
493  // initialize transactors
494  mp_S_AXI_transactor = NULL;
495  mp_s_axi_awlen_converter = NULL;
496  mp_s_axi_awlock_converter = NULL;
497  mp_s_axi_arlen_converter = NULL;
498  mp_s_axi_arlock_converter = NULL;
499  mp_M_AXI_transactor = NULL;
500 
501  // initialize socket stubs
502 
503 }
504 
505 void design_1_auto_pc_1::before_end_of_elaboration()
506 {
507  // configure 'S_AXI' transactor
508 
509  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "S_AXI_TLM_MODE") != 1)
510  {
511  // Instantiate Socket Stubs
512 
513  // 'S_AXI' transactor parameters
514  xsc::common_cpp::properties S_AXI_transactor_param_props;
515  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
516  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
517  S_AXI_transactor_param_props.addLong("ID_WIDTH", "12");
518  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
519  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
520  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
521  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
522  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
523  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
524  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
525  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
526  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
527  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
528  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
529  S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
530  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
531  S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
532  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
533  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
534  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
535  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
536  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
537  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
538  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
539  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
540  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
541  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
542  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
543  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
544  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
545  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
546  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
547 
548  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
549 
550  // S_AXI' transactor ports
551 
552  mp_S_AXI_transactor->AWID(s_axi_awid);
553  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
554  mp_s_axi_awlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_awlen_converter");
555  mp_s_axi_awlen_converter->vector_in(s_axi_awlen);
556  mp_s_axi_awlen_converter->vector_out(m_s_axi_awlen_converter_signal);
557  mp_S_AXI_transactor->AWLEN(m_s_axi_awlen_converter_signal);
558  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
559  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
560  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_awlock_converter");
561  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
562  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
563  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
564  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
565  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
566  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
567  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
568  mp_S_AXI_transactor->AWREADY(s_axi_awready);
569  mp_S_AXI_transactor->WDATA(s_axi_wdata);
570  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
571  mp_S_AXI_transactor->WLAST(s_axi_wlast);
572  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
573  mp_S_AXI_transactor->WREADY(s_axi_wready);
574  mp_S_AXI_transactor->BID(s_axi_bid);
575  mp_S_AXI_transactor->BRESP(s_axi_bresp);
576  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
577  mp_S_AXI_transactor->BREADY(s_axi_bready);
578  mp_S_AXI_transactor->ARID(s_axi_arid);
579  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
580  mp_s_axi_arlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_arlen_converter");
581  mp_s_axi_arlen_converter->vector_in(s_axi_arlen);
582  mp_s_axi_arlen_converter->vector_out(m_s_axi_arlen_converter_signal);
583  mp_S_AXI_transactor->ARLEN(m_s_axi_arlen_converter_signal);
584  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
585  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
586  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_arlock_converter");
587  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
588  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
589  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
590  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
591  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
592  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
593  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
594  mp_S_AXI_transactor->ARREADY(s_axi_arready);
595  mp_S_AXI_transactor->RID(s_axi_rid);
596  mp_S_AXI_transactor->RDATA(s_axi_rdata);
597  mp_S_AXI_transactor->RRESP(s_axi_rresp);
598  mp_S_AXI_transactor->RLAST(s_axi_rlast);
599  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
600  mp_S_AXI_transactor->RREADY(s_axi_rready);
601  mp_S_AXI_transactor->CLK(aclk);
602  mp_S_AXI_transactor->RST(aresetn);
603 
604  // S_AXI' transactor sockets
605 
606  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
607  mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
608  }
609  else
610  {
611  }
612 
613  // configure 'M_AXI' transactor
614 
615  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "M_AXI_TLM_MODE") != 1)
616  {
617  // Instantiate Socket Stubs
618 
619  // 'M_AXI' transactor parameters
620  xsc::common_cpp::properties M_AXI_transactor_param_props;
621  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
622  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
623  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
624  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
625  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
626  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
627  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
628  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
629  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
630  M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
631  M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
632  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
633  M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
634  M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
635  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
636  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
637  M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
638  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
639  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
640  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
641  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
642  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
643  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
644  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
645  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
646  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
647  M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
648  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
649  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
650  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
651  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
652  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
653 
654  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
655 
656  // M_AXI' transactor ports
657 
658  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
659  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
660  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
661  mp_M_AXI_transactor->AWREADY(m_axi_awready);
662  mp_M_AXI_transactor->WDATA(m_axi_wdata);
663  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
664  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
665  mp_M_AXI_transactor->WREADY(m_axi_wready);
666  mp_M_AXI_transactor->BRESP(m_axi_bresp);
667  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
668  mp_M_AXI_transactor->BREADY(m_axi_bready);
669  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
670  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
671  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
672  mp_M_AXI_transactor->ARREADY(m_axi_arready);
673  mp_M_AXI_transactor->RDATA(m_axi_rdata);
674  mp_M_AXI_transactor->RRESP(m_axi_rresp);
675  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
676  mp_M_AXI_transactor->RREADY(m_axi_rready);
677  mp_M_AXI_transactor->CLK(aclk);
678  mp_M_AXI_transactor->RST(aresetn);
679 
680  // M_AXI' transactor sockets
681 
682  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
683  mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
684  }
685  else
686  {
687  }
688 
689 }
690 
691 #endif // RIVIERA
692 
693 
694 
695 
696 #ifdef VCSSYSTEMC
697 design_1_auto_pc_1::design_1_auto_pc_1(const sc_core::sc_module_name& nm) : design_1_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wid("s_axi_wid"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
698 {
699  // initialize pins
700  mp_impl->aclk(aclk);
701  mp_impl->aresetn(aresetn);
702 
703  // initialize transactors
704  mp_S_AXI_transactor = NULL;
705  mp_s_axi_awlen_converter = NULL;
706  mp_s_axi_awlock_converter = NULL;
707  mp_s_axi_arlen_converter = NULL;
708  mp_s_axi_arlock_converter = NULL;
709  mp_M_AXI_transactor = NULL;
710 
711  // Instantiate Socket Stubs
712 
713  // configure S_AXI_transactor
714  xsc::common_cpp::properties S_AXI_transactor_param_props;
715  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
716  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
717  S_AXI_transactor_param_props.addLong("ID_WIDTH", "12");
718  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
719  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
720  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
721  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
722  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
723  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
724  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
725  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
726  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
727  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
728  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
729  S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
730  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
731  S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
732  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
733  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
734  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
735  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
736  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
737  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
738  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
739  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
740  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
741  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
742  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
743  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
744  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
745  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
746  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
747 
748  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
749  mp_S_AXI_transactor->AWID(s_axi_awid);
750  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
751  mp_s_axi_awlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_awlen_converter");
752  mp_s_axi_awlen_converter->vector_in(s_axi_awlen);
753  mp_s_axi_awlen_converter->vector_out(m_s_axi_awlen_converter_signal);
754  mp_S_AXI_transactor->AWLEN(m_s_axi_awlen_converter_signal);
755  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
756  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
757  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_awlock_converter");
758  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
759  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
760  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
761  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
762  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
763  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
764  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
765  mp_S_AXI_transactor->AWREADY(s_axi_awready);
766  mp_S_AXI_transactor->WDATA(s_axi_wdata);
767  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
768  mp_S_AXI_transactor->WLAST(s_axi_wlast);
769  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
770  mp_S_AXI_transactor->WREADY(s_axi_wready);
771  mp_S_AXI_transactor->BID(s_axi_bid);
772  mp_S_AXI_transactor->BRESP(s_axi_bresp);
773  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
774  mp_S_AXI_transactor->BREADY(s_axi_bready);
775  mp_S_AXI_transactor->ARID(s_axi_arid);
776  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
777  mp_s_axi_arlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_arlen_converter");
778  mp_s_axi_arlen_converter->vector_in(s_axi_arlen);
779  mp_s_axi_arlen_converter->vector_out(m_s_axi_arlen_converter_signal);
780  mp_S_AXI_transactor->ARLEN(m_s_axi_arlen_converter_signal);
781  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
782  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
783  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_arlock_converter");
784  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
785  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
786  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
787  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
788  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
789  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
790  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
791  mp_S_AXI_transactor->ARREADY(s_axi_arready);
792  mp_S_AXI_transactor->RID(s_axi_rid);
793  mp_S_AXI_transactor->RDATA(s_axi_rdata);
794  mp_S_AXI_transactor->RRESP(s_axi_rresp);
795  mp_S_AXI_transactor->RLAST(s_axi_rlast);
796  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
797  mp_S_AXI_transactor->RREADY(s_axi_rready);
798  mp_S_AXI_transactor->CLK(aclk);
799  mp_S_AXI_transactor->RST(aresetn);
800  // configure M_AXI_transactor
801  xsc::common_cpp::properties M_AXI_transactor_param_props;
802  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
803  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
804  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
805  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
806  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
807  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
808  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
809  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
810  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
811  M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
812  M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
813  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
814  M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
815  M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
816  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
817  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
818  M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
819  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
820  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
821  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
822  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
823  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
824  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
825  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
826  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
827  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
828  M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
829  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
830  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
831  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
832  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
833  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
834 
835  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
836  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
837  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
838  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
839  mp_M_AXI_transactor->AWREADY(m_axi_awready);
840  mp_M_AXI_transactor->WDATA(m_axi_wdata);
841  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
842  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
843  mp_M_AXI_transactor->WREADY(m_axi_wready);
844  mp_M_AXI_transactor->BRESP(m_axi_bresp);
845  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
846  mp_M_AXI_transactor->BREADY(m_axi_bready);
847  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
848  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
849  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
850  mp_M_AXI_transactor->ARREADY(m_axi_arready);
851  mp_M_AXI_transactor->RDATA(m_axi_rdata);
852  mp_M_AXI_transactor->RRESP(m_axi_rresp);
853  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
854  mp_M_AXI_transactor->RREADY(m_axi_rready);
855  mp_M_AXI_transactor->CLK(aclk);
856  mp_M_AXI_transactor->RST(aresetn);
857 
858  // initialize transactors stubs
859  S_AXI_transactor_target_wr_socket_stub = nullptr;
860  S_AXI_transactor_target_rd_socket_stub = nullptr;
861  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
862  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
863 
864 }
865 
866 void design_1_auto_pc_1::before_end_of_elaboration()
867 {
868  // configure 'S_AXI' transactor
869  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "S_AXI_TLM_MODE") != 1)
870  {
871  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
872  mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
873 
874  }
875  else
876  {
877  S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
878  S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
879  S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
880  S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
881  mp_S_AXI_transactor->disable_transactor();
882  }
883 
884  // configure 'M_AXI' transactor
885  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "M_AXI_TLM_MODE") != 1)
886  {
887  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
888  mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
889 
890  }
891  else
892  {
893  M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
894  M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
895  M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
896  M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
897  mp_M_AXI_transactor->disable_transactor();
898  }
899 
900 }
901 
902 #endif // VCSSYSTEMC
903 
904 
905 
906 
907 #ifdef MTI_SYSTEMC
908 design_1_auto_pc_1::design_1_auto_pc_1(const sc_core::sc_module_name& nm) : design_1_auto_pc_1_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_awid("s_axi_awid"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awqos("s_axi_awqos"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wid("s_axi_wid"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bid("s_axi_bid"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_arid("s_axi_arid"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rid("s_axi_rid"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_awaddr("m_axi_awaddr"), m_axi_awprot("m_axi_awprot"), m_axi_awvalid("m_axi_awvalid"), m_axi_awready("m_axi_awready"), m_axi_wdata("m_axi_wdata"), m_axi_wstrb("m_axi_wstrb"), m_axi_wvalid("m_axi_wvalid"), m_axi_wready("m_axi_wready"), m_axi_bresp("m_axi_bresp"), m_axi_bvalid("m_axi_bvalid"), m_axi_bready("m_axi_bready"), m_axi_araddr("m_axi_araddr"), m_axi_arprot("m_axi_arprot"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready")
909 {
910  // initialize pins
911  mp_impl->aclk(aclk);
912  mp_impl->aresetn(aresetn);
913 
914  // initialize transactors
915  mp_S_AXI_transactor = NULL;
916  mp_s_axi_awlen_converter = NULL;
917  mp_s_axi_awlock_converter = NULL;
918  mp_s_axi_arlen_converter = NULL;
919  mp_s_axi_arlock_converter = NULL;
920  mp_M_AXI_transactor = NULL;
921 
922  // Instantiate Socket Stubs
923 
924  // configure S_AXI_transactor
925  xsc::common_cpp::properties S_AXI_transactor_param_props;
926  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
927  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
928  S_AXI_transactor_param_props.addLong("ID_WIDTH", "12");
929  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
930  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
931  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
932  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
933  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
934  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
935  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
936  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
937  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
938  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
939  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
940  S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
941  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
942  S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
943  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
944  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
945  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
946  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
947  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
948  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
949  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
950  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
951  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
952  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
953  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
954  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
955  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
956  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
957  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
958 
959  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
960  mp_S_AXI_transactor->AWID(s_axi_awid);
961  mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
962  mp_s_axi_awlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_awlen_converter");
963  mp_s_axi_awlen_converter->vector_in(s_axi_awlen);
964  mp_s_axi_awlen_converter->vector_out(m_s_axi_awlen_converter_signal);
965  mp_S_AXI_transactor->AWLEN(m_s_axi_awlen_converter_signal);
966  mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
967  mp_S_AXI_transactor->AWBURST(s_axi_awburst);
968  mp_s_axi_awlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_awlock_converter");
969  mp_s_axi_awlock_converter->vector_in(s_axi_awlock);
970  mp_s_axi_awlock_converter->scalar_out(m_s_axi_awlock_converter_signal);
971  mp_S_AXI_transactor->AWLOCK(m_s_axi_awlock_converter_signal);
972  mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
973  mp_S_AXI_transactor->AWPROT(s_axi_awprot);
974  mp_S_AXI_transactor->AWQOS(s_axi_awqos);
975  mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
976  mp_S_AXI_transactor->AWREADY(s_axi_awready);
977  mp_S_AXI_transactor->WDATA(s_axi_wdata);
978  mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
979  mp_S_AXI_transactor->WLAST(s_axi_wlast);
980  mp_S_AXI_transactor->WVALID(s_axi_wvalid);
981  mp_S_AXI_transactor->WREADY(s_axi_wready);
982  mp_S_AXI_transactor->BID(s_axi_bid);
983  mp_S_AXI_transactor->BRESP(s_axi_bresp);
984  mp_S_AXI_transactor->BVALID(s_axi_bvalid);
985  mp_S_AXI_transactor->BREADY(s_axi_bready);
986  mp_S_AXI_transactor->ARID(s_axi_arid);
987  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
988  mp_s_axi_arlen_converter = new xsc::common::vector2vector_converter<4,8>("s_axi_arlen_converter");
989  mp_s_axi_arlen_converter->vector_in(s_axi_arlen);
990  mp_s_axi_arlen_converter->vector_out(m_s_axi_arlen_converter_signal);
991  mp_S_AXI_transactor->ARLEN(m_s_axi_arlen_converter_signal);
992  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
993  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
994  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<2>("s_axi_arlock_converter");
995  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
996  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
997  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
998  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
999  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
1000  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
1001  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
1002  mp_S_AXI_transactor->ARREADY(s_axi_arready);
1003  mp_S_AXI_transactor->RID(s_axi_rid);
1004  mp_S_AXI_transactor->RDATA(s_axi_rdata);
1005  mp_S_AXI_transactor->RRESP(s_axi_rresp);
1006  mp_S_AXI_transactor->RLAST(s_axi_rlast);
1007  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
1008  mp_S_AXI_transactor->RREADY(s_axi_rready);
1009  mp_S_AXI_transactor->CLK(aclk);
1010  mp_S_AXI_transactor->RST(aresetn);
1011  // configure M_AXI_transactor
1012  xsc::common_cpp::properties M_AXI_transactor_param_props;
1013  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
1014  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
1015  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
1016  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
1017  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
1018  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
1019  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
1020  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
1021  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
1022  M_AXI_transactor_param_props.addLong("HAS_BURST", "0");
1023  M_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
1024  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
1025  M_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
1026  M_AXI_transactor_param_props.addLong("HAS_QOS", "0");
1027  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
1028  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
1029  M_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
1030  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
1031  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
1032  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
1033  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
1034  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
1035  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "4");
1036  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "4");
1037  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
1038  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
1039  M_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
1040  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
1041  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
1042  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
1043  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
1044  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
1045 
1046  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
1047  mp_M_AXI_transactor->AWADDR(m_axi_awaddr);
1048  mp_M_AXI_transactor->AWPROT(m_axi_awprot);
1049  mp_M_AXI_transactor->AWVALID(m_axi_awvalid);
1050  mp_M_AXI_transactor->AWREADY(m_axi_awready);
1051  mp_M_AXI_transactor->WDATA(m_axi_wdata);
1052  mp_M_AXI_transactor->WSTRB(m_axi_wstrb);
1053  mp_M_AXI_transactor->WVALID(m_axi_wvalid);
1054  mp_M_AXI_transactor->WREADY(m_axi_wready);
1055  mp_M_AXI_transactor->BRESP(m_axi_bresp);
1056  mp_M_AXI_transactor->BVALID(m_axi_bvalid);
1057  mp_M_AXI_transactor->BREADY(m_axi_bready);
1058  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
1059  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
1060  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
1061  mp_M_AXI_transactor->ARREADY(m_axi_arready);
1062  mp_M_AXI_transactor->RDATA(m_axi_rdata);
1063  mp_M_AXI_transactor->RRESP(m_axi_rresp);
1064  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
1065  mp_M_AXI_transactor->RREADY(m_axi_rready);
1066  mp_M_AXI_transactor->CLK(aclk);
1067  mp_M_AXI_transactor->RST(aresetn);
1068 
1069  // initialize transactors stubs
1070  S_AXI_transactor_target_wr_socket_stub = nullptr;
1071  S_AXI_transactor_target_rd_socket_stub = nullptr;
1072  M_AXI_transactor_initiator_wr_socket_stub = nullptr;
1073  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
1074 
1075 }
1076 
1077 void design_1_auto_pc_1::before_end_of_elaboration()
1078 {
1079  // configure 'S_AXI' transactor
1080  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "S_AXI_TLM_MODE") != 1)
1081  {
1082  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
1083  mp_impl->target_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
1084 
1085  }
1086  else
1087  {
1088  S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
1089  S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
1090  S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
1091  S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
1092  mp_S_AXI_transactor->disable_transactor();
1093  }
1094 
1095  // configure 'M_AXI' transactor
1096  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_1", "M_AXI_TLM_MODE") != 1)
1097  {
1098  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
1099  mp_impl->initiator_wr_socket->bind(*(mp_M_AXI_transactor->wr_socket));
1100 
1101  }
1102  else
1103  {
1104  M_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
1105  M_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M_AXI_transactor->wr_socket));
1106  M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
1107  M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
1108  mp_M_AXI_transactor->disable_transactor();
1109  }
1110 
1111 }
1112 
1113 #endif // MTI_SYSTEMC
1114 
1115 
1116 
1117 
1118 design_1_auto_pc_1::~design_1_auto_pc_1()
1119 {
1120  delete mp_S_AXI_transactor;
1121  delete mp_s_axi_awlen_converter;
1122  delete mp_s_axi_awlock_converter;
1123  delete mp_s_axi_arlen_converter;
1124  delete mp_s_axi_arlock_converter;
1125 
1126  delete mp_M_AXI_transactor;
1127 
1128 }
1129 
1130 #ifdef MTI_SYSTEMC
1131 SC_MODULE_EXPORT(design_1_auto_pc_1);
1132 #endif
1133 
1134 #ifdef XM_SYSTEMC
1135 XMSC_MODULE_EXPORT(design_1_auto_pc_1);
1136 #endif
1137 
1138 #ifdef RIVIERA
1139 SC_MODULE_EXPORT(design_1_auto_pc_1);
1140 #endif
1141 
s_axi_awready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire s_axi_awready
Definition: axi_vip_v1_1_vl_rfs.sv:109
s_axi_bready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire s_axi_bready
Definition: axi_vip_v1_1_vl_rfs.sv:125
m_axi_wdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > m_axi_wdata
Definition: axi_vip_v1_1_vl_rfs.sv:168
s_axi_arburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > s_axi_arburst
Definition: axi_vip_v1_1_vl_rfs.sv:132
s_axi_arlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > s_axi_arlen
Definition: axi_vip_v1_1_vl_rfs.sv:130
axi_protocol_converter::aclk
sc_in< bool > aclk
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:16
m_axi_wvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire m_axi_wvalid
Definition: axi_vip_v1_1_vl_rfs.sv:172
m_axi_bvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire m_axi_bvalid
Definition: axi_vip_v1_1_vl_rfs.sv:179
s_axi_awqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > s_axi_awqos
Definition: axi_vip_v1_1_vl_rfs.sv:106
s_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire s_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:148
s_axi_rlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire s_axi_rlast
Definition: axi_vip_v1_1_vl_rfs.sv:146
m_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire m_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:195
m_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire m_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:203
s_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire s_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:149
s_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire s_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:139
s_axi_awid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > s_axi_awid
Definition: axi_vip_v1_1_vl_rfs.sv:97
s_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > s_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:145
s_axi_bresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > s_axi_bresp
Definition: axi_vip_v1_1_vl_rfs.sv:122
s_axi_awprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > s_axi_awprot
Definition: axi_vip_v1_1_vl_rfs.sv:104
s_axi_arid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > s_axi_arid
Definition: axi_vip_v1_1_vl_rfs.sv:128
axi_protocol_converter::aresetn
sc_in< bool > aresetn
Definition: design_1_auto_pc_0/src/axi_protocol_converter.h:17
s_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire s_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:140
s_axi_wdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > s_axi_wdata
Definition: axi_vip_v1_1_vl_rfs.sv:113
m_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire output wire m_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:205
m_axi_awaddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > m_axi_awaddr
Definition: axi_vip_v1_1_vl_rfs.sv:153
s_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > s_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:129
s_axi_awaddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > s_axi_awaddr
Definition: axi_vip_v1_1_vl_rfs.sv:98
m_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > m_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:200
design_1_auto_pc_1_sc
Definition: design_1_auto_pc_1_sc.h:70
m_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire m_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:194
s_axi_wstrb
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > s_axi_wstrb
Definition: axi_vip_v1_1_vl_rfs.sv:114
aresetn
DowngradeIPIdentifiedWarnings module input wire input wire aresetn
Definition: axi_vip_v1_1_vl_rfs.sv:94
s_axi_arlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > s_axi_arlock
Definition: axi_vip_v1_1_vl_rfs.sv:133
s_axi_rid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > s_axi_rid
Definition: axi_vip_v1_1_vl_rfs.sv:143
s_axi_awvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire s_axi_awvalid
Definition: axi_vip_v1_1_vl_rfs.sv:108
s_axi_wready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire s_axi_wready
Definition: axi_vip_v1_1_vl_rfs.sv:118
m_axi_bresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > m_axi_bresp
Definition: axi_vip_v1_1_vl_rfs.sv:177
m_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > m_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:199
m_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > m_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:184
s_axi_wlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire s_axi_wlast
Definition: axi_vip_v1_1_vl_rfs.sv:115
m_axi_awvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire m_axi_awvalid
Definition: axi_vip_v1_1_vl_rfs.sv:163
s_axi_awsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > s_axi_awsize
Definition: axi_vip_v1_1_vl_rfs.sv:100
m_axi_bready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire m_axi_bready
Definition: axi_vip_v1_1_vl_rfs.sv:180
s_axi_wvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire s_axi_wvalid
Definition: axi_vip_v1_1_vl_rfs.sv:117
s_axi_bid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > s_axi_bid
Definition: axi_vip_v1_1_vl_rfs.sv:121
s_axi_awburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > s_axi_awburst
Definition: axi_vip_v1_1_vl_rfs.sv:101
m_axi_wready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire m_axi_wready
Definition: axi_vip_v1_1_vl_rfs.sv:173
design_1_auto_pc_1.h
s_axi_arcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > s_axi_arcache
Definition: axi_vip_v1_1_vl_rfs.sv:134
s_axi_awcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > s_axi_awcache
Definition: axi_vip_v1_1_vl_rfs.sv:103
m_axi_awready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire m_axi_awready
Definition: axi_vip_v1_1_vl_rfs.sv:164
m_axi_awprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > m_axi_awprot
Definition: axi_vip_v1_1_vl_rfs.sv:159
design_1_auto_pc_0_sc::mp_impl
axi_protocol_converter * mp_impl
Definition: design_1_auto_pc_0_sc.h:89
s_axi_wid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > s_axi_wid
Definition: axi_vip_v1_1_vl_rfs.sv:112
m_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > m_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:190
s_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > s_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:144
m_axi_wstrb
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > m_axi_wstrb
Definition: axi_vip_v1_1_vl_rfs.sv:169
design_1_auto_pc_1_sc.h
s_axi_awlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > s_axi_awlen
Definition: axi_vip_v1_1_vl_rfs.sv:99
s_axi_arsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > s_axi_arsize
Definition: axi_vip_v1_1_vl_rfs.sv:131
s_axi_awlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > s_axi_awlock
Definition: axi_vip_v1_1_vl_rfs.sv:102
s_axi_arqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > s_axi_arqos
Definition: axi_vip_v1_1_vl_rfs.sv:137
s_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > s_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:135
s_axi_bvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire s_axi_bvalid
Definition: axi_vip_v1_1_vl_rfs.sv:124