vt52-fpga  1.0.0 Initial
vt52-fpga is a serial terminal implemented on a FPGA
usb_uart_i40.v
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1 /*
2  usb_uart_i40
3 
4  Simple wrapper around the usb_uart which incorporates the Pin driver logic
5  so this doesn't clutter the top level circuit
6 
7  The layer above has to assert the Host Pull Up line
8 
9  ----------------------------------------------------
10  usb_uart_i40 u_u_i40 (
11  .clk_48mhz (clk_48mhz),
12  .reset (reset),
13 
14  // pins
15  .pin_usb_p( pin_usb_p ),
16  .pin_usb_n( pin_usb_n ),
17 
18  // uart pipeline in
19  .uart_in_data( uart_in_data ),
20  .uart_in_valid( uart_in_valid ),
21  .uart_in_ready( uart_in_ready ),
22 
23  // uart pipeline out
24  .uart_out_data( uart_out_data ),
25  .uart_out_valid( uart_out_valid ),
26  .uart_out_ready( uart_out_ready ),
27  );
28 
29 */
30 
31 module usb_uart (
32  input clk_48mhz,
33  input reset,
34 
35  // USB pins
36  inout pin_usb_p,
37  inout pin_usb_n,
38 
39  // uart pipeline in (out of the device, into the host)
40  input [7:0] uart_in_data,
41  input uart_in_valid,
42  output uart_in_ready,
43 
44  // uart pipeline out (into the device, out of the host)
45  output [7:0] uart_out_data,
46  output uart_out_valid,
47  input uart_out_ready,
48 
49  output [11:0] debug
50 );
51 
52  wire usb_p_tx;
53  wire usb_n_tx;
54  wire usb_p_rx;
55  wire usb_n_rx;
56  wire usb_tx_en;
57 
58  //wire [3:0] debug;
59 
60  usb_uart_core uart (
61  .clk_48mhz (clk_48mhz),
62  .reset (reset),
63 
64  // pins - these must be connected properly to the outside world. See below.
65  .usb_p_tx(usb_p_tx),
66  .usb_n_tx(usb_n_tx),
67  .usb_p_rx(usb_p_rx),
68  .usb_n_rx(usb_n_rx),
69  .usb_tx_en(usb_tx_en),
70 
71  // uart pipeline in
72  .uart_in_data( uart_in_data ),
73  .uart_in_valid( uart_in_valid ),
74  .uart_in_ready( uart_in_ready ),
75 
76  // uart pipeline out
77  .uart_out_data( uart_out_data ),
78  .uart_out_valid( uart_out_valid ),
79  .uart_out_ready( uart_out_ready ),
80 
81  .debug( debug )
82  );
83 
84  wire usb_p_in;
85  wire usb_n_in;
86 
87  assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
88  assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;
89 
90  SB_IO #(
91  .PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT
92  .PULLUP(1'b 0)
93  ) iobuf_usbp (
94  .PACKAGE_PIN(pin_usb_p),
95  .OUTPUT_ENABLE(usb_tx_en),
96  .D_OUT_0(usb_p_tx),
97  .D_IN_0(usb_p_in)
98  );
99 
100  SB_IO #(
101  .PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT
102  .PULLUP(1'b 0)
103  ) iobuf_usbn (
104  .PACKAGE_PIN(pin_usb_n),
105  .OUTPUT_ENABLE(usb_tx_en),
106  .D_OUT_0(usb_n_tx),
107  .D_IN_0(usb_n_in)
108  );
109 
110 endmodule
uart
module uart(parameter DATA_WIDTH=8)(input wire clk
usb_uart_core
module usb_uart_core(input clk_48mhz, input reset, output usb_p_tx, output usb_n_tx, input usb_p_rx, input usb_n_rx, output usb_tx_en, input[8] uart_in_data, input uart_in_valid, output uart_in_ready, output[8] uart_out_data, output uart_out_valid, input uart_out_ready, output[11:0] debug)
Definition: usb_uart_core.v:126
usb_uart
module usb_uart(input clk_48mhz, input reset, inout pin_usb_p, inout pin_usb_n, input[8] uart_in_data, input uart_in_valid, output uart_in_ready, output[8] uart_out_data, output uart_out_valid, input uart_out_ready, output[11:0] debug)
Definition: usb_uart_i40.v:31