SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_auto_pc_0.h
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1 #ifndef IP_DESIGN_1_AUTO_PC_0_H_
2 #define IP_DESIGN_1_AUTO_PC_0_H_
3 
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51 
52 
53 #ifndef XTLM
54 #include "xtlm.h"
55 #endif
56 #ifndef SYSTEMC_INCLUDED
57 #include <systemc>
58 #endif
59 
60 #if defined(_MSC_VER)
61 #define DllExport __declspec(dllexport)
62 #elif defined(__GNUC__)
63 #define DllExport __attribute__ ((visibility("default")))
64 #else
65 #define DllExport
66 #endif
67 
68 #include "design_1_auto_pc_0_sc.h"
69 
70 
71 
72 
73 #ifdef XILINX_SIMULATOR
74 #include "utils/xtlm_aximm_initiator_stub.h"
75 #include "utils/xtlm_aximm_target_stub.h"
76 class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
77 {
78 public:
79 
80  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
81  virtual ~design_1_auto_pc_0();
82 
83  // module pin-to-pin RTL interface
84 
85  sc_core::sc_in< bool > aclk;
86  sc_core::sc_in< bool > aresetn;
87  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
88  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
89  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
90  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
91  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
92  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
93  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
94  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
95  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
96  sc_core::sc_in< bool > s_axi_arvalid;
97  sc_core::sc_out< bool > s_axi_arready;
98  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
99  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
100  sc_core::sc_out< bool > s_axi_rlast;
101  sc_core::sc_out< bool > s_axi_rvalid;
102  sc_core::sc_in< bool > s_axi_rready;
103  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
104  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
105  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
106  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
107  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
108  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
109  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
110  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
111  sc_core::sc_out< bool > m_axi_arvalid;
112  sc_core::sc_in< bool > m_axi_arready;
113  sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
114  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
115  sc_core::sc_in< bool > m_axi_rlast;
116  sc_core::sc_in< bool > m_axi_rvalid;
117  sc_core::sc_out< bool > m_axi_rready;
118 
119  // Dummy Signals for IP Ports
120 
121 
122 protected:
123 
124  virtual void before_end_of_elaboration();
125 
126 private:
127 
128  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
129  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
130  sc_signal< bool > m_s_axi_arlock_converter_signal;
131  xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
132  xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
133  sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
134  xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
135  sc_signal< bool > m_m_axi_arlock_converter_signal;
136  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
137  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
138 
139 };
140 #endif // XILINX_SIMULATOR
141 
142 
143 
144 
145 #ifdef XM_SYSTEMC
146 #include "utils/xtlm_aximm_initiator_stub.h"
147 #include "utils/xtlm_aximm_target_stub.h"
148 class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
149 {
150 public:
151 
152  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
153  virtual ~design_1_auto_pc_0();
154 
155  // module pin-to-pin RTL interface
156 
157  sc_core::sc_in< bool > aclk;
158  sc_core::sc_in< bool > aresetn;
159  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
160  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
161  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
162  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
163  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
164  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
165  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
166  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
167  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
168  sc_core::sc_in< bool > s_axi_arvalid;
169  sc_core::sc_out< bool > s_axi_arready;
170  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
171  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
172  sc_core::sc_out< bool > s_axi_rlast;
173  sc_core::sc_out< bool > s_axi_rvalid;
174  sc_core::sc_in< bool > s_axi_rready;
175  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
176  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
177  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
178  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
179  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
180  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
181  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
182  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
183  sc_core::sc_out< bool > m_axi_arvalid;
184  sc_core::sc_in< bool > m_axi_arready;
185  sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
186  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
187  sc_core::sc_in< bool > m_axi_rlast;
188  sc_core::sc_in< bool > m_axi_rvalid;
189  sc_core::sc_out< bool > m_axi_rready;
190 
191  // Dummy Signals for IP Ports
192 
193 
194 protected:
195 
196  virtual void before_end_of_elaboration();
197 
198 private:
199 
200  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
201  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
202  sc_signal< bool > m_s_axi_arlock_converter_signal;
203  xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
204  xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
205  sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
206  xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
207  sc_signal< bool > m_m_axi_arlock_converter_signal;
208  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
209  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
210 
211 };
212 #endif // XM_SYSTEMC
213 
214 
215 
216 
217 #ifdef RIVIERA
218 #include "utils/xtlm_aximm_initiator_stub.h"
219 #include "utils/xtlm_aximm_target_stub.h"
220 class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
221 {
222 public:
223 
224  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
225  virtual ~design_1_auto_pc_0();
226 
227  // module pin-to-pin RTL interface
228 
229  sc_core::sc_in< bool > aclk;
230  sc_core::sc_in< bool > aresetn;
231  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
232  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
233  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
234  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
235  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
236  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
237  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
238  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
239  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
240  sc_core::sc_in< bool > s_axi_arvalid;
241  sc_core::sc_out< bool > s_axi_arready;
242  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
243  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
244  sc_core::sc_out< bool > s_axi_rlast;
245  sc_core::sc_out< bool > s_axi_rvalid;
246  sc_core::sc_in< bool > s_axi_rready;
247  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
248  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
249  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
250  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
251  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
252  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
253  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
254  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
255  sc_core::sc_out< bool > m_axi_arvalid;
256  sc_core::sc_in< bool > m_axi_arready;
257  sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
258  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
259  sc_core::sc_in< bool > m_axi_rlast;
260  sc_core::sc_in< bool > m_axi_rvalid;
261  sc_core::sc_out< bool > m_axi_rready;
262 
263  // Dummy Signals for IP Ports
264 
265 
266 protected:
267 
268  virtual void before_end_of_elaboration();
269 
270 private:
271 
272  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
273  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
274  sc_signal< bool > m_s_axi_arlock_converter_signal;
275  xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
276  xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
277  sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
278  xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
279  sc_signal< bool > m_m_axi_arlock_converter_signal;
280  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
281  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
282 
283 };
284 #endif // RIVIERA
285 
286 
287 
288 
289 #ifdef VCSSYSTEMC
290 #include "utils/xtlm_aximm_initiator_stub.h"
291 
292 #include "utils/xtlm_aximm_target_stub.h"
293 
294 class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
295 {
296 public:
297 
298  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
299  virtual ~design_1_auto_pc_0();
300 
301  // module pin-to-pin RTL interface
302 
303  sc_core::sc_in< bool > aclk;
304  sc_core::sc_in< bool > aresetn;
305  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
306  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
307  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
308  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
309  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
310  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
311  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
312  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
313  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
314  sc_core::sc_in< bool > s_axi_arvalid;
315  sc_core::sc_out< bool > s_axi_arready;
316  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
317  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
318  sc_core::sc_out< bool > s_axi_rlast;
319  sc_core::sc_out< bool > s_axi_rvalid;
320  sc_core::sc_in< bool > s_axi_rready;
321  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
322  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
323  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
324  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
325  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
326  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
327  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
328  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
329  sc_core::sc_out< bool > m_axi_arvalid;
330  sc_core::sc_in< bool > m_axi_arready;
331  sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
332  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
333  sc_core::sc_in< bool > m_axi_rlast;
334  sc_core::sc_in< bool > m_axi_rvalid;
335  sc_core::sc_out< bool > m_axi_rready;
336 
337  // Dummy Signals for IP Ports
338 
339 
340 protected:
341 
342  virtual void before_end_of_elaboration();
343 
344 private:
345 
346  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
347  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
348  sc_signal< bool > m_s_axi_arlock_converter_signal;
349  xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
350  xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
351  sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
352  xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
353  sc_signal< bool > m_m_axi_arlock_converter_signal;
354 
355  // Transactor stubs
356  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
357  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
358 
359  // Socket stubs
360  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
361  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
362 
363 };
364 #endif // VCSSYSTEMC
365 
366 
367 
368 
369 #ifdef MTI_SYSTEMC
370 #include "utils/xtlm_aximm_initiator_stub.h"
371 
372 #include "utils/xtlm_aximm_target_stub.h"
373 
374 class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
375 {
376 public:
377 
378  design_1_auto_pc_0(const sc_core::sc_module_name& nm);
379  virtual ~design_1_auto_pc_0();
380 
381  // module pin-to-pin RTL interface
382 
383  sc_core::sc_in< bool > aclk;
384  sc_core::sc_in< bool > aresetn;
385  sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
386  sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
387  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
388  sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
389  sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
390  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
391  sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
392  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
393  sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
394  sc_core::sc_in< bool > s_axi_arvalid;
395  sc_core::sc_out< bool > s_axi_arready;
396  sc_core::sc_out< sc_dt::sc_bv<64> > s_axi_rdata;
397  sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
398  sc_core::sc_out< bool > s_axi_rlast;
399  sc_core::sc_out< bool > s_axi_rvalid;
400  sc_core::sc_in< bool > s_axi_rready;
401  sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
402  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
403  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
404  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
405  sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
406  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
407  sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
408  sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
409  sc_core::sc_out< bool > m_axi_arvalid;
410  sc_core::sc_in< bool > m_axi_arready;
411  sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
412  sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
413  sc_core::sc_in< bool > m_axi_rlast;
414  sc_core::sc_in< bool > m_axi_rvalid;
415  sc_core::sc_out< bool > m_axi_rready;
416 
417  // Dummy Signals for IP Ports
418 
419 
420 protected:
421 
422  virtual void before_end_of_elaboration();
423 
424 private:
425 
426  xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
427  xsc::common::vectorN2scalar_converter<1>* mp_s_axi_arlock_converter;
428  sc_signal< bool > m_s_axi_arlock_converter_signal;
429  xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
430  xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
431  sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
432  xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
433  sc_signal< bool > m_m_axi_arlock_converter_signal;
434 
435  // Transactor stubs
436  xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
437  xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
438 
439  // Socket stubs
440  xtlm::xtlm_aximm_initiator_stub* mp_S_AXI_wr_socket_stub;
441  xtlm::xtlm_aximm_target_stub* mp_M_AXI_wr_socket_stub;
442 
443 };
444 #endif // MTI_SYSTEMC
445 #endif // IP_DESIGN_1_AUTO_PC_0_H_
s_axi_arburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > s_axi_arburst
Definition: axi_vip_v1_1_vl_rfs.sv:132
s_axi_arlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > s_axi_arlen
Definition: axi_vip_v1_1_vl_rfs.sv:130
m_axi_arsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > m_axi_arsize
Definition: axi_vip_v1_1_vl_rfs.sv:186
s_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire s_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:148
s_axi_arregion
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > s_axi_arregion
Definition: axi_vip_v1_1_vl_rfs.sv:136
s_axi_rlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire s_axi_rlast
Definition: axi_vip_v1_1_vl_rfs.sv:146
m_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire m_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:195
m_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire m_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:203
s_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire s_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:149
s_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire s_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:139
s_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > s_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:145
m_axi_arlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > m_axi_arlock
Definition: axi_vip_v1_1_vl_rfs.sv:188
m_axi_arburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > m_axi_arburst
Definition: axi_vip_v1_1_vl_rfs.sv:187
s_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire s_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:140
m_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire output wire m_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:205
s_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > s_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:129
m_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > m_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:200
m_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire m_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:194
aresetn
DowngradeIPIdentifiedWarnings module input wire input wire aresetn
Definition: axi_vip_v1_1_vl_rfs.sv:94
s_axi_arlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > s_axi_arlock
Definition: axi_vip_v1_1_vl_rfs.sv:133
m_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > m_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:199
m_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > m_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:184
DllExport
#define DllExport
Definition: design_1_auto_pc_0.h:65
m_axi_arlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > m_axi_arlen
Definition: axi_vip_v1_1_vl_rfs.sv:185
design_1_auto_pc_0_sc
Definition: design_1_auto_pc_0_sc.h:70
m_axi_rlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire m_axi_rlast
Definition: axi_vip_v1_1_vl_rfs.sv:201
s_axi_arcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > s_axi_arcache
Definition: axi_vip_v1_1_vl_rfs.sv:134
m_axi_arcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > m_axi_arcache
Definition: axi_vip_v1_1_vl_rfs.sv:189
design_1_auto_pc_0_sc.h
m_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > m_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:190
s_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > s_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:144
m_axi_arqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > m_axi_arqos
Definition: axi_vip_v1_1_vl_rfs.sv:192
s_axi_arsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > s_axi_arsize
Definition: axi_vip_v1_1_vl_rfs.sv:131
s_axi_arqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > s_axi_arqos
Definition: axi_vip_v1_1_vl_rfs.sv:137
s_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > s_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:135