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SimpleVOut
1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
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Go to the documentation of this file.
52 #define OPCODE_EXIT 0U
53 #define OPCODE_CLEAR 1U
54 #define OPCODE_WRITE 2U
55 #define OPCODE_MASKWRITE 3U
56 #define OPCODE_MASKPOLL 4U
57 #define OPCODE_MASKDELAY 5U
58 #define NEW_PS7_ERR_CODE 1
61 #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
62 #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
63 #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
64 #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
65 #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
66 #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
69 #define PS7_INIT_SUCCESS (0) // 0 is success in good old C
70 #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
71 #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
72 #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
73 #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
74 #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
78 #define PCW_SILICON_VERSION_1 0
79 #define PCW_SILICON_VERSION_2 1
80 #define PCW_SILICON_VERSION_3 2
83 #define PS7_POST_CONFIG
87 #define APU_FREQ 666666687
88 #define DDR_FREQ 533333374
89 #define DCI_FREQ 10158730
90 #define QSPI_FREQ 10000000
91 #define SMC_FREQ 100000000
92 #define ENET0_FREQ 25000000
93 #define ENET1_FREQ 10000000
94 #define USB0_FREQ 60000000
95 #define USB1_FREQ 60000000
96 #define SDIO_FREQ 100000000
97 #define UART_FREQ 100000000
98 #define SPI_FREQ 10000000
99 #define I2C_FREQ 111111115
100 #define WDT_FREQ 111111115
101 #define TTC_FREQ 50000000
102 #define CAN_FREQ 10000000
103 #define PCAP_FREQ 200000000
104 #define TPIU_FREQ 200000000
105 #define FPGA0_FREQ 125000000
106 #define FPGA1_FREQ 25000000
107 #define FPGA2_FREQ 33333336
108 #define FPGA3_FREQ 100000000
112 #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
113 #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
114 #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
115 #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int get_number_of_cycles_for_delay(unsigned int delay)
void perf_reset_and_start_timer()
char * getPS7MessageInfo(unsigned key)
void perf_reset_clock(void)
unsigned long * ps7_peripherals_init_data
unsigned long * ps7_clock_init_data
unsigned long * ps7_mio_init_data
unsigned long * ps7_ddr_init_data
do we need to make this name more unique ?
int ps7_config(unsigned long *)
void perf_start_clock(void)
unsigned long * ps7_pll_init_data
void perf_disable_clock(void)