SimpleVOut
1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_xlconstant_0_0.h
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:xlconstant:1.1
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// IP Revision: 1
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#ifndef _design_1_xlconstant_0_0_H_
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#define _design_1_xlconstant_0_0_H_
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#include "
xlconstant_v1_1_7.h
"
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#include "systemc.h"
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class
design_1_xlconstant_0_0
:
public
sc_module {
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public
:
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xlconstant_v1_1_7<4,1>
mod
;
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sc_out< sc_bv<4> >
dout
;
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design_1_xlconstant_0_0
(sc_core::sc_module_name name);
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};
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#endif
design_1_xlconstant_0_0::dout
sc_out< sc_bv< 4 > > dout
Definition:
design_1_xlconstant_0_0.h:61
design_1_xlconstant_0_0
Definition:
design_1_xlconstant_0_0.h:58
design_1_xlconstant_0_0::mod
xlconstant_v1_1_7< 4, 1 > mod
Definition:
design_1_xlconstant_0_0.h:60
xlconstant_v1_1_7.h
design_1_xlconstant_0_0::design_1_xlconstant_0_0
design_1_xlconstant_0_0(sc_core::sc_module_name name)
Definition:
design_1_xlconstant_0_0.cpp:58
Demos
myproj
project_1.gen
sources_1
bd
design_1
ip
design_1_xlconstant_0_0
sim
design_1_xlconstant_0_0.h
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