SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_xlconstant_0_0.h
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49 
50 // IP VLNV: xilinx.com:ip:xlconstant:1.1
51 // IP Revision: 1
52 
53 #ifndef _design_1_xlconstant_0_0_H_
54 #define _design_1_xlconstant_0_0_H_
55 
56 #include "xlconstant_v1_1_7.h"
57 #include "systemc.h"
58 class design_1_xlconstant_0_0 : public sc_module {
59  public:
60 xlconstant_v1_1_7<4,1> mod;
61  sc_out< sc_bv<4> > dout;
62 design_1_xlconstant_0_0 (sc_core::sc_module_name name);
63  };
64 
65 #endif
design_1_xlconstant_0_0::dout
sc_out< sc_bv< 4 > > dout
Definition: design_1_xlconstant_0_0.h:61
design_1_xlconstant_0_0
Definition: design_1_xlconstant_0_0.h:58
design_1_xlconstant_0_0::mod
xlconstant_v1_1_7< 4, 1 > mod
Definition: design_1_xlconstant_0_0.h:60
xlconstant_v1_1_7.h
design_1_xlconstant_0_0::design_1_xlconstant_0_0
design_1_xlconstant_0_0(sc_core::sc_module_name name)
Definition: design_1_xlconstant_0_0.cpp:58