SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_clk_wiz_0_ooc.xdc
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2 # file: design_1_clk_wiz_0_ooc.xdc
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51 #################
52 #DEFAULT CLOCK CONSTRAINTS
53 
54 ############################################################
55 # Clock Period Constraints #
56 ############################################################
57 #create_clock -period 8.000 [get_ports clk_in1]
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