design_1_clk_wiz_0.xdc

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# file: design_1_clk_wiz_0.xdc
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# Input clock periods. These duplicate the values entered for the
# input clocks. You can use these to time your system. If required
# commented constraints can be used in the top level xdc 
#----------------------------------------------------------------
# Connect to input port when clock capable pin is selected for input
create_clock -period 8.000 [get_ports clk_in1]
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.08
 
 
set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]