SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_auto_pc_0.cpp
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48 
49 
50 #include "design_1_auto_pc_0_sc.h"
51 
52 #include "design_1_auto_pc_0.h"
53 
54 #include "axi_protocol_converter.h"
55 
56 #include <map>
57 #include <string>
58 
59 
60 
61 
62 
63 #ifdef XILINX_SIMULATOR
64 design_1_auto_pc_0::design_1_auto_pc_0(const sc_core::sc_module_name& nm) : design_1_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
65 {
66 
67  // initialize pins
68  mp_impl->aclk(aclk);
69  mp_impl->aresetn(aresetn);
70 
71  // initialize transactors
72  mp_S_AXI_transactor = NULL;
73  mp_s_axi_arlock_converter = NULL;
74  mp_M_AXI_transactor = NULL;
75  mp_m_axi_arlen_converter = NULL;
76  mp_m_axi_arlock_converter = NULL;
77 
78  // initialize socket stubs
79  mp_S_AXI_wr_socket_stub = NULL;
80  mp_M_AXI_wr_socket_stub = NULL;
81 
82 }
83 
84 void design_1_auto_pc_0::before_end_of_elaboration()
85 {
86  // configure 'S_AXI' transactor
87 
88  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "S_AXI_TLM_MODE") != 1)
89  {
90  // Instantiate Socket Stubs
91  mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
92 
93  // 'S_AXI' transactor parameters
94  xsc::common_cpp::properties S_AXI_transactor_param_props;
95  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
96  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
97  S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
98  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
99  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
100  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
101  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
102  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
103  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
104  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
105  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
106  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
107  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
108  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
109  S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
110  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
111  S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
112  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
113  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
114  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
115  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
116  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
117  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
118  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
119  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
120  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
121  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
122  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
123  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
124  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
125  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
126  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
127 
128  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
129 
130  // S_AXI' transactor ports
131 
132  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
133  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
134  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
135  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
136  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
137  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
138  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
139  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
140  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
141  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
142  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
143  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
144  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
145  mp_S_AXI_transactor->ARREADY(s_axi_arready);
146  mp_S_AXI_transactor->RDATA(s_axi_rdata);
147  mp_S_AXI_transactor->RRESP(s_axi_rresp);
148  mp_S_AXI_transactor->RLAST(s_axi_rlast);
149  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
150  mp_S_AXI_transactor->RREADY(s_axi_rready);
151  mp_S_AXI_transactor->CLK(aclk);
152  mp_S_AXI_transactor->RST(aresetn);
153 
154  // S_AXI' transactor sockets
155 
156  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
157  mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
158  }
159  else
160  {
161  }
162 
163  // configure 'M_AXI' transactor
164 
165  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "M_AXI_TLM_MODE") != 1)
166  {
167  // Instantiate Socket Stubs
168  mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
169 
170  // 'M_AXI' transactor parameters
171  xsc::common_cpp::properties M_AXI_transactor_param_props;
172  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
173  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
174  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
175  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
176  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
177  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
178  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
179  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
180  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
181  M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
182  M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
183  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
184  M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
185  M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
186  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
187  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
188  M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
189  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
190  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
191  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
192  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
193  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
194  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
195  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
196  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
197  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
198  M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
199  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
200  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
201  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
202  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
203  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
204 
205  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
206 
207  // M_AXI' transactor ports
208 
209  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
210  mp_m_axi_arlen_converter = new xsc::common::vector2vector_converter<8,4>("m_axi_arlen_converter");
211  mp_m_axi_arlen_converter->vector_in(m_m_axi_arlen_converter_signal);
212  mp_m_axi_arlen_converter->vector_out(m_axi_arlen);
213  mp_M_AXI_transactor->ARLEN(m_m_axi_arlen_converter_signal);
214  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
215  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
216  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<2>("m_axi_arlock_converter");
217  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
218  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
219  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
220  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
221  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
222  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
223  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
224  mp_M_AXI_transactor->ARREADY(m_axi_arready);
225  mp_M_AXI_transactor->RDATA(m_axi_rdata);
226  mp_M_AXI_transactor->RRESP(m_axi_rresp);
227  mp_M_AXI_transactor->RLAST(m_axi_rlast);
228  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
229  mp_M_AXI_transactor->RREADY(m_axi_rready);
230  mp_M_AXI_transactor->CLK(aclk);
231  mp_M_AXI_transactor->RST(aresetn);
232 
233  // M_AXI' transactor sockets
234 
235  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
236  mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
237  }
238  else
239  {
240  }
241 
242 }
243 
244 #endif // XILINX_SIMULATOR
245 
246 
247 
248 
249 #ifdef XM_SYSTEMC
250 design_1_auto_pc_0::design_1_auto_pc_0(const sc_core::sc_module_name& nm) : design_1_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
251 {
252 
253  // initialize pins
254  mp_impl->aclk(aclk);
255  mp_impl->aresetn(aresetn);
256 
257  // initialize transactors
258  mp_S_AXI_transactor = NULL;
259  mp_s_axi_arlock_converter = NULL;
260  mp_M_AXI_transactor = NULL;
261  mp_m_axi_arlen_converter = NULL;
262  mp_m_axi_arlock_converter = NULL;
263 
264  // initialize socket stubs
265  mp_S_AXI_wr_socket_stub = NULL;
266  mp_M_AXI_wr_socket_stub = NULL;
267 
268 }
269 
270 void design_1_auto_pc_0::before_end_of_elaboration()
271 {
272  // configure 'S_AXI' transactor
273 
274  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "S_AXI_TLM_MODE") != 1)
275  {
276  // Instantiate Socket Stubs
277  mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
278 
279  // 'S_AXI' transactor parameters
280  xsc::common_cpp::properties S_AXI_transactor_param_props;
281  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
282  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
283  S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
284  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
285  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
286  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
287  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
288  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
289  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
290  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
291  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
292  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
293  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
294  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
295  S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
296  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
297  S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
298  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
299  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
300  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
301  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
302  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
303  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
304  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
305  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
306  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
307  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
308  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
309  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
310  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
311  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
312  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
313 
314  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
315 
316  // S_AXI' transactor ports
317 
318  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
319  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
320  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
321  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
322  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
323  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
324  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
325  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
326  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
327  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
328  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
329  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
330  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
331  mp_S_AXI_transactor->ARREADY(s_axi_arready);
332  mp_S_AXI_transactor->RDATA(s_axi_rdata);
333  mp_S_AXI_transactor->RRESP(s_axi_rresp);
334  mp_S_AXI_transactor->RLAST(s_axi_rlast);
335  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
336  mp_S_AXI_transactor->RREADY(s_axi_rready);
337  mp_S_AXI_transactor->CLK(aclk);
338  mp_S_AXI_transactor->RST(aresetn);
339 
340  // S_AXI' transactor sockets
341 
342  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
343  mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
344  }
345  else
346  {
347  }
348 
349  // configure 'M_AXI' transactor
350 
351  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "M_AXI_TLM_MODE") != 1)
352  {
353  // Instantiate Socket Stubs
354  mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
355 
356  // 'M_AXI' transactor parameters
357  xsc::common_cpp::properties M_AXI_transactor_param_props;
358  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
359  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
360  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
361  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
362  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
363  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
364  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
365  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
366  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
367  M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
368  M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
369  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
370  M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
371  M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
372  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
373  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
374  M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
375  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
376  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
377  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
378  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
379  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
380  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
381  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
382  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
383  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
384  M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
385  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
386  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
387  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
388  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
389  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
390 
391  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
392 
393  // M_AXI' transactor ports
394 
395  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
396  mp_m_axi_arlen_converter = new xsc::common::vector2vector_converter<8,4>("m_axi_arlen_converter");
397  mp_m_axi_arlen_converter->vector_in(m_m_axi_arlen_converter_signal);
398  mp_m_axi_arlen_converter->vector_out(m_axi_arlen);
399  mp_M_AXI_transactor->ARLEN(m_m_axi_arlen_converter_signal);
400  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
401  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
402  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<2>("m_axi_arlock_converter");
403  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
404  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
405  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
406  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
407  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
408  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
409  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
410  mp_M_AXI_transactor->ARREADY(m_axi_arready);
411  mp_M_AXI_transactor->RDATA(m_axi_rdata);
412  mp_M_AXI_transactor->RRESP(m_axi_rresp);
413  mp_M_AXI_transactor->RLAST(m_axi_rlast);
414  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
415  mp_M_AXI_transactor->RREADY(m_axi_rready);
416  mp_M_AXI_transactor->CLK(aclk);
417  mp_M_AXI_transactor->RST(aresetn);
418 
419  // M_AXI' transactor sockets
420 
421  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
422  mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
423  }
424  else
425  {
426  }
427 
428 }
429 
430 #endif // XM_SYSTEMC
431 
432 
433 
434 
435 #ifdef RIVIERA
436 design_1_auto_pc_0::design_1_auto_pc_0(const sc_core::sc_module_name& nm) : design_1_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
437 {
438 
439  // initialize pins
440  mp_impl->aclk(aclk);
441  mp_impl->aresetn(aresetn);
442 
443  // initialize transactors
444  mp_S_AXI_transactor = NULL;
445  mp_s_axi_arlock_converter = NULL;
446  mp_M_AXI_transactor = NULL;
447  mp_m_axi_arlen_converter = NULL;
448  mp_m_axi_arlock_converter = NULL;
449 
450  // initialize socket stubs
451  mp_S_AXI_wr_socket_stub = NULL;
452  mp_M_AXI_wr_socket_stub = NULL;
453 
454 }
455 
456 void design_1_auto_pc_0::before_end_of_elaboration()
457 {
458  // configure 'S_AXI' transactor
459 
460  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "S_AXI_TLM_MODE") != 1)
461  {
462  // Instantiate Socket Stubs
463  mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
464 
465  // 'S_AXI' transactor parameters
466  xsc::common_cpp::properties S_AXI_transactor_param_props;
467  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
468  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
469  S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
470  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
471  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
472  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
473  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
474  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
475  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
476  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
477  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
478  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
479  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
480  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
481  S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
482  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
483  S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
484  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
485  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
486  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
487  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
488  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
489  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
490  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
491  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
492  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
493  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
494  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
495  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
496  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
497  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
498  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
499 
500  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
501 
502  // S_AXI' transactor ports
503 
504  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
505  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
506  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
507  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
508  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
509  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
510  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
511  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
512  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
513  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
514  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
515  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
516  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
517  mp_S_AXI_transactor->ARREADY(s_axi_arready);
518  mp_S_AXI_transactor->RDATA(s_axi_rdata);
519  mp_S_AXI_transactor->RRESP(s_axi_rresp);
520  mp_S_AXI_transactor->RLAST(s_axi_rlast);
521  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
522  mp_S_AXI_transactor->RREADY(s_axi_rready);
523  mp_S_AXI_transactor->CLK(aclk);
524  mp_S_AXI_transactor->RST(aresetn);
525 
526  // S_AXI' transactor sockets
527 
528  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
529  mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
530  }
531  else
532  {
533  }
534 
535  // configure 'M_AXI' transactor
536 
537  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "M_AXI_TLM_MODE") != 1)
538  {
539  // Instantiate Socket Stubs
540  mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
541 
542  // 'M_AXI' transactor parameters
543  xsc::common_cpp::properties M_AXI_transactor_param_props;
544  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
545  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
546  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
547  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
548  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
549  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
550  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
551  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
552  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
553  M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
554  M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
555  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
556  M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
557  M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
558  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
559  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
560  M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
561  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
562  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
563  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
564  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
565  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
566  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
567  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
568  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
569  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
570  M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
571  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
572  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
573  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
574  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
575  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
576 
577  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
578 
579  // M_AXI' transactor ports
580 
581  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
582  mp_m_axi_arlen_converter = new xsc::common::vector2vector_converter<8,4>("m_axi_arlen_converter");
583  mp_m_axi_arlen_converter->vector_in(m_m_axi_arlen_converter_signal);
584  mp_m_axi_arlen_converter->vector_out(m_axi_arlen);
585  mp_M_AXI_transactor->ARLEN(m_m_axi_arlen_converter_signal);
586  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
587  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
588  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<2>("m_axi_arlock_converter");
589  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
590  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
591  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
592  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
593  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
594  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
595  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
596  mp_M_AXI_transactor->ARREADY(m_axi_arready);
597  mp_M_AXI_transactor->RDATA(m_axi_rdata);
598  mp_M_AXI_transactor->RRESP(m_axi_rresp);
599  mp_M_AXI_transactor->RLAST(m_axi_rlast);
600  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
601  mp_M_AXI_transactor->RREADY(m_axi_rready);
602  mp_M_AXI_transactor->CLK(aclk);
603  mp_M_AXI_transactor->RST(aresetn);
604 
605  // M_AXI' transactor sockets
606 
607  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
608  mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
609  }
610  else
611  {
612  }
613 
614 }
615 
616 #endif // RIVIERA
617 
618 
619 
620 
621 #ifdef VCSSYSTEMC
622 design_1_auto_pc_0::design_1_auto_pc_0(const sc_core::sc_module_name& nm) : design_1_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
623 {
624  // initialize pins
625  mp_impl->aclk(aclk);
626  mp_impl->aresetn(aresetn);
627 
628  // initialize transactors
629  mp_S_AXI_transactor = NULL;
630  mp_s_axi_arlock_converter = NULL;
631  mp_M_AXI_transactor = NULL;
632  mp_m_axi_arlen_converter = NULL;
633  mp_m_axi_arlock_converter = NULL;
634 
635  // Instantiate Socket Stubs
636  mp_S_AXI_wr_socket_stub = NULL;
637  mp_M_AXI_wr_socket_stub = NULL;
638 
639  // configure S_AXI_transactor
640  xsc::common_cpp::properties S_AXI_transactor_param_props;
641  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
642  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
643  S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
644  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
645  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
646  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
647  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
648  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
649  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
650  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
651  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
652  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
653  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
654  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
655  S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
656  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
657  S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
658  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
659  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
660  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
661  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
662  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
663  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
664  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
665  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
666  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
667  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
668  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
669  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
670  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
671  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
672  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
673 
674  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
675  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
676  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
677  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
678  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
679  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
680  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
681  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
682  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
683  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
684  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
685  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
686  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
687  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
688  mp_S_AXI_transactor->ARREADY(s_axi_arready);
689  mp_S_AXI_transactor->RDATA(s_axi_rdata);
690  mp_S_AXI_transactor->RRESP(s_axi_rresp);
691  mp_S_AXI_transactor->RLAST(s_axi_rlast);
692  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
693  mp_S_AXI_transactor->RREADY(s_axi_rready);
694  mp_S_AXI_transactor->CLK(aclk);
695  mp_S_AXI_transactor->RST(aresetn);
696  // configure M_AXI_transactor
697  xsc::common_cpp::properties M_AXI_transactor_param_props;
698  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
699  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
700  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
701  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
702  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
703  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
704  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
705  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
706  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
707  M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
708  M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
709  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
710  M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
711  M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
712  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
713  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
714  M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
715  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
716  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
717  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
718  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
719  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
720  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
721  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
722  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
723  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
724  M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
725  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
726  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
727  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
728  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
729  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
730 
731  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
732  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
733  mp_m_axi_arlen_converter = new xsc::common::vector2vector_converter<8,4>("m_axi_arlen_converter");
734  mp_m_axi_arlen_converter->vector_in(m_m_axi_arlen_converter_signal);
735  mp_m_axi_arlen_converter->vector_out(m_axi_arlen);
736  mp_M_AXI_transactor->ARLEN(m_m_axi_arlen_converter_signal);
737  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
738  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
739  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<2>("m_axi_arlock_converter");
740  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
741  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
742  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
743  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
744  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
745  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
746  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
747  mp_M_AXI_transactor->ARREADY(m_axi_arready);
748  mp_M_AXI_transactor->RDATA(m_axi_rdata);
749  mp_M_AXI_transactor->RRESP(m_axi_rresp);
750  mp_M_AXI_transactor->RLAST(m_axi_rlast);
751  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
752  mp_M_AXI_transactor->RREADY(m_axi_rready);
753  mp_M_AXI_transactor->CLK(aclk);
754  mp_M_AXI_transactor->RST(aresetn);
755 
756  // initialize transactors stubs
757  S_AXI_transactor_target_rd_socket_stub = nullptr;
758  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
759 
760 }
761 
762 void design_1_auto_pc_0::before_end_of_elaboration()
763 {
764  // configure 'S_AXI' transactor
765  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "S_AXI_TLM_MODE") != 1)
766  {
767  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
768  mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
769  mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
770 
771  }
772  else
773  {
774  S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
775  S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
776  mp_S_AXI_transactor->disable_transactor();
777  }
778 
779  // configure 'M_AXI' transactor
780  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "M_AXI_TLM_MODE") != 1)
781  {
782  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
783  mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
784  mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
785 
786  }
787  else
788  {
789  M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
790  M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
791  mp_M_AXI_transactor->disable_transactor();
792  }
793 
794 }
795 
796 #endif // VCSSYSTEMC
797 
798 
799 
800 
801 #ifdef MTI_SYSTEMC
802 design_1_auto_pc_0::design_1_auto_pc_0(const sc_core::sc_module_name& nm) : design_1_auto_pc_0_sc(nm), aclk("aclk"), aresetn("aresetn"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arregion("s_axi_arregion"), s_axi_arqos("s_axi_arqos"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), m_axi_araddr("m_axi_araddr"), m_axi_arlen("m_axi_arlen"), m_axi_arsize("m_axi_arsize"), m_axi_arburst("m_axi_arburst"), m_axi_arlock("m_axi_arlock"), m_axi_arcache("m_axi_arcache"), m_axi_arprot("m_axi_arprot"), m_axi_arqos("m_axi_arqos"), m_axi_arvalid("m_axi_arvalid"), m_axi_arready("m_axi_arready"), m_axi_rdata("m_axi_rdata"), m_axi_rresp("m_axi_rresp"), m_axi_rlast("m_axi_rlast"), m_axi_rvalid("m_axi_rvalid"), m_axi_rready("m_axi_rready"),mp_S_AXI_wr_socket_stub(nullptr),mp_M_AXI_wr_socket_stub(nullptr)
803 {
804  // initialize pins
805  mp_impl->aclk(aclk);
806  mp_impl->aresetn(aresetn);
807 
808  // initialize transactors
809  mp_S_AXI_transactor = NULL;
810  mp_s_axi_arlock_converter = NULL;
811  mp_M_AXI_transactor = NULL;
812  mp_m_axi_arlen_converter = NULL;
813  mp_m_axi_arlock_converter = NULL;
814 
815  // Instantiate Socket Stubs
816  mp_S_AXI_wr_socket_stub = NULL;
817  mp_M_AXI_wr_socket_stub = NULL;
818 
819  // configure S_AXI_transactor
820  xsc::common_cpp::properties S_AXI_transactor_param_props;
821  S_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
822  S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
823  S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
824  S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
825  S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
826  S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
827  S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
828  S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
829  S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
830  S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
831  S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
832  S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
833  S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
834  S_AXI_transactor_param_props.addLong("HAS_QOS", "1");
835  S_AXI_transactor_param_props.addLong("HAS_REGION", "1");
836  S_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
837  S_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
838  S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
839  S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
840  S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
841  S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
842  S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
843  S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
844  S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
845  S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
846  S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
847  S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
848  S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
849  S_AXI_transactor_param_props.addFloat("PHASE", "0.000");
850  S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
851  S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
852  S_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
853 
854  mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<64,32,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
855  mp_S_AXI_transactor->ARADDR(s_axi_araddr);
856  mp_S_AXI_transactor->ARLEN(s_axi_arlen);
857  mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
858  mp_S_AXI_transactor->ARBURST(s_axi_arburst);
859  mp_s_axi_arlock_converter = new xsc::common::vectorN2scalar_converter<1>("s_axi_arlock_converter");
860  mp_s_axi_arlock_converter->vector_in(s_axi_arlock);
861  mp_s_axi_arlock_converter->scalar_out(m_s_axi_arlock_converter_signal);
862  mp_S_AXI_transactor->ARLOCK(m_s_axi_arlock_converter_signal);
863  mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
864  mp_S_AXI_transactor->ARPROT(s_axi_arprot);
865  mp_S_AXI_transactor->ARREGION(s_axi_arregion);
866  mp_S_AXI_transactor->ARQOS(s_axi_arqos);
867  mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
868  mp_S_AXI_transactor->ARREADY(s_axi_arready);
869  mp_S_AXI_transactor->RDATA(s_axi_rdata);
870  mp_S_AXI_transactor->RRESP(s_axi_rresp);
871  mp_S_AXI_transactor->RLAST(s_axi_rlast);
872  mp_S_AXI_transactor->RVALID(s_axi_rvalid);
873  mp_S_AXI_transactor->RREADY(s_axi_rready);
874  mp_S_AXI_transactor->CLK(aclk);
875  mp_S_AXI_transactor->RST(aresetn);
876  // configure M_AXI_transactor
877  xsc::common_cpp::properties M_AXI_transactor_param_props;
878  M_AXI_transactor_param_props.addLong("DATA_WIDTH", "64");
879  M_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
880  M_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
881  M_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
882  M_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
883  M_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
884  M_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
885  M_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
886  M_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
887  M_AXI_transactor_param_props.addLong("HAS_BURST", "1");
888  M_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
889  M_AXI_transactor_param_props.addLong("HAS_PROT", "1");
890  M_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
891  M_AXI_transactor_param_props.addLong("HAS_QOS", "1");
892  M_AXI_transactor_param_props.addLong("HAS_REGION", "0");
893  M_AXI_transactor_param_props.addLong("HAS_WSTRB", "0");
894  M_AXI_transactor_param_props.addLong("HAS_BRESP", "0");
895  M_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
896  M_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "1");
897  M_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "8");
898  M_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "8");
899  M_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "16");
900  M_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
901  M_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
902  M_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
903  M_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
904  M_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
905  M_AXI_transactor_param_props.addLong("HAS_RESET", "1");
906  M_AXI_transactor_param_props.addFloat("PHASE", "0.000");
907  M_AXI_transactor_param_props.addString("PROTOCOL", "AXI3");
908  M_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_ONLY");
909  M_AXI_transactor_param_props.addString("CLK_DOMAIN", "design_1_processing_system7_0_0_FCLK_CLK0");
910 
911  mp_M_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>("M_AXI_transactor", M_AXI_transactor_param_props);
912  mp_M_AXI_transactor->ARADDR(m_axi_araddr);
913  mp_m_axi_arlen_converter = new xsc::common::vector2vector_converter<8,4>("m_axi_arlen_converter");
914  mp_m_axi_arlen_converter->vector_in(m_m_axi_arlen_converter_signal);
915  mp_m_axi_arlen_converter->vector_out(m_axi_arlen);
916  mp_M_AXI_transactor->ARLEN(m_m_axi_arlen_converter_signal);
917  mp_M_AXI_transactor->ARSIZE(m_axi_arsize);
918  mp_M_AXI_transactor->ARBURST(m_axi_arburst);
919  mp_m_axi_arlock_converter = new xsc::common::scalar2vectorN_converter<2>("m_axi_arlock_converter");
920  mp_m_axi_arlock_converter->scalar_in(m_m_axi_arlock_converter_signal);
921  mp_m_axi_arlock_converter->vector_out(m_axi_arlock);
922  mp_M_AXI_transactor->ARLOCK(m_m_axi_arlock_converter_signal);
923  mp_M_AXI_transactor->ARCACHE(m_axi_arcache);
924  mp_M_AXI_transactor->ARPROT(m_axi_arprot);
925  mp_M_AXI_transactor->ARQOS(m_axi_arqos);
926  mp_M_AXI_transactor->ARVALID(m_axi_arvalid);
927  mp_M_AXI_transactor->ARREADY(m_axi_arready);
928  mp_M_AXI_transactor->RDATA(m_axi_rdata);
929  mp_M_AXI_transactor->RRESP(m_axi_rresp);
930  mp_M_AXI_transactor->RLAST(m_axi_rlast);
931  mp_M_AXI_transactor->RVALID(m_axi_rvalid);
932  mp_M_AXI_transactor->RREADY(m_axi_rready);
933  mp_M_AXI_transactor->CLK(aclk);
934  mp_M_AXI_transactor->RST(aresetn);
935 
936  // initialize transactors stubs
937  S_AXI_transactor_target_rd_socket_stub = nullptr;
938  M_AXI_transactor_initiator_rd_socket_stub = nullptr;
939 
940 }
941 
942 void design_1_auto_pc_0::before_end_of_elaboration()
943 {
944  // configure 'S_AXI' transactor
945  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "S_AXI_TLM_MODE") != 1)
946  {
947  mp_impl->target_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
948  mp_S_AXI_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket", 0);
949  mp_impl->target_wr_socket->bind(mp_S_AXI_wr_socket_stub->initiator_socket);
950 
951  }
952  else
953  {
954  S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
955  S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
956  mp_S_AXI_transactor->disable_transactor();
957  }
958 
959  // configure 'M_AXI' transactor
960  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "M_AXI_TLM_MODE") != 1)
961  {
962  mp_impl->initiator_rd_socket->bind(*(mp_M_AXI_transactor->rd_socket));
963  mp_M_AXI_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket", 0);
964  mp_impl->initiator_wr_socket->bind(mp_M_AXI_wr_socket_stub->target_socket);
965 
966  }
967  else
968  {
969  M_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
970  M_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M_AXI_transactor->rd_socket));
971  mp_M_AXI_transactor->disable_transactor();
972  }
973 
974 }
975 
976 #endif // MTI_SYSTEMC
977 
978 
979 
980 
981 design_1_auto_pc_0::~design_1_auto_pc_0()
982 {
983  delete mp_S_AXI_transactor;
984  delete mp_s_axi_arlock_converter;
985  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "S_AXI_TLM_MODE") != 1)
986  {
987  delete mp_S_AXI_wr_socket_stub;
988  }
989 
990  delete mp_M_AXI_transactor;
991  delete mp_m_axi_arlen_converter;
992  delete mp_m_axi_arlock_converter;
993  if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("design_1_auto_pc_0", "M_AXI_TLM_MODE") != 1)
994  {
995  delete mp_M_AXI_wr_socket_stub;
996  }
997 
998 }
999 
1000 #ifdef MTI_SYSTEMC
1001 SC_MODULE_EXPORT(design_1_auto_pc_0);
1002 #endif
1003 
1004 #ifdef XM_SYSTEMC
1005 XMSC_MODULE_EXPORT(design_1_auto_pc_0);
1006 #endif
1007 
1008 #ifdef RIVIERA
1009 SC_MODULE_EXPORT(design_1_auto_pc_0);
1010 SC_REGISTER_BV(64);
1011 #endif
1012 
design_1_auto_pc_0.h
s_axi_arburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > s_axi_arburst
Definition: axi_vip_v1_1_vl_rfs.sv:132
s_axi_arlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > s_axi_arlen
Definition: axi_vip_v1_1_vl_rfs.sv:130
m_axi_arsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > m_axi_arsize
Definition: axi_vip_v1_1_vl_rfs.sv:186
s_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire s_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:148
s_axi_arregion
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > s_axi_arregion
Definition: axi_vip_v1_1_vl_rfs.sv:136
s_axi_rlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire s_axi_rlast
Definition: axi_vip_v1_1_vl_rfs.sv:146
m_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire m_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:195
m_axi_rvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire m_axi_rvalid
Definition: axi_vip_v1_1_vl_rfs.sv:203
s_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire s_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:149
s_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire s_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:139
s_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > s_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:145
m_axi_arlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > m_axi_arlock
Definition: axi_vip_v1_1_vl_rfs.sv:188
m_axi_arburst
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > m_axi_arburst
Definition: axi_vip_v1_1_vl_rfs.sv:187
s_axi_arready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire s_axi_arready
Definition: axi_vip_v1_1_vl_rfs.sv:140
m_axi_rready
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire input wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > input wire output wire m_axi_rready
Definition: axi_vip_v1_1_vl_rfs.sv:205
s_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > s_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:129
m_axi_rresp
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > m_axi_rresp
Definition: axi_vip_v1_1_vl_rfs.sv:200
m_axi_arvalid
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire m_axi_arvalid
Definition: axi_vip_v1_1_vl_rfs.sv:194
aresetn
DowngradeIPIdentifiedWarnings module input wire input wire aresetn
Definition: axi_vip_v1_1_vl_rfs.sv:94
s_axi_arlock
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > s_axi_arlock
Definition: axi_vip_v1_1_vl_rfs.sv:133
m_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > m_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:199
m_axi_araddr
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > m_axi_araddr
Definition: axi_vip_v1_1_vl_rfs.sv:184
m_axi_arlen
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > m_axi_arlen
Definition: axi_vip_v1_1_vl_rfs.sv:185
design_1_auto_pc_0_sc
Definition: design_1_auto_pc_0_sc.h:70
m_axi_rlast
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_RDATA_WIDTH-1:0 > input wire< 2-1:0 > input wire m_axi_rlast
Definition: axi_vip_v1_1_vl_rfs.sv:201
s_axi_arcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > s_axi_arcache
Definition: axi_vip_v1_1_vl_rfs.sv:134
m_axi_arcache
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > m_axi_arcache
Definition: axi_vip_v1_1_vl_rfs.sv:189
design_1_auto_pc_0_sc.h
m_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > m_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:190
s_axi_rdata
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > s_axi_rdata
Definition: axi_vip_v1_1_vl_rfs.sv:144
m_axi_arqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_RDATA_WIDTH-1:0 > output wire< 2-1:0 > output wire output wire< C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > output wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > output wire input wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH-1:0 > output wire< C_AXI_WDATA_WIDTH/8==0?0:C_AXI_WDATA_WIDTH/8-1:0 > output wire output wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< 2-1:0 > input wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > output wire< C_AXI_ADDR_WIDTH-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > output wire< 3-1:0 > output wire< 2-1:0 > output wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > output wire< 4-1:0 > output wire< 3-1:0 > output wire< 4-1:0 > output wire< 4-1:0 > m_axi_arqos
Definition: axi_vip_v1_1_vl_rfs.sv:192
s_axi_arsize
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > s_axi_arsize
Definition: axi_vip_v1_1_vl_rfs.sv:131
s_axi_arqos
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > s_axi_arqos
Definition: axi_vip_v1_1_vl_rfs.sv:137
s_axi_arprot
DowngradeIPIdentifiedWarnings module input wire input wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > input wire< 4-1:0 > input wire< 4-1:0 > input wire< C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0 > input wire output wire input wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH-1:0 > input wire< C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0 > input wire input wire< C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0 > input wire output wire output wire< C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0 > output wire< 2-1:0 > output wire< C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0 > output wire input wire input wire< C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0 > input wire< C_AXI_ADDR_WIDTH-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 4 :8) -1:0 > input wire< 3-1:0 > input wire< 2-1:0 > input wire<((C_AXI_PROTOCOL==1) ? 2 :1) -1:0 > input wire< 4-1:0 > input wire< 3-1:0 > s_axi_arprot
Definition: axi_vip_v1_1_vl_rfs.sv:135