SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
xilinx_zynq Class Reference

#include <xilinx-zynq.h>

Inheritance diagram for xilinx_zynq:
Collaboration diagram for xilinx_zynq:

Public Member Functions

 xilinx_zynq (sc_core::sc_module_name name, const char *sk_descr)
 

Public Attributes

tlm_utils::simple_initiator_socket< remoteport_tlm_memory_master > * m_axi_gp [2]
 
tlm_utils::simple_target_socket< remoteport_tlm_memory_slave > * s_axi_gp [2]
 
tlm_utils::simple_target_socket< remoteport_tlm_memory_slave > * s_axi_hp [4]
 
tlm_utils::simple_target_socket< remoteport_tlm_memory_slave > * s_axi_acp
 
sc_vector< sc_signal< bool > > pl2ps_irq
 
sc_vector< sc_signal< bool > > ps2pl_irq
 
sc_vector< sc_signal< bool > > ps2pl_rst
 

Private Attributes

remoteport_tlm_memory_master rp_m_axi_gp0
 
remoteport_tlm_memory_master rp_m_axi_gp1
 
remoteport_tlm_memory_slave rp_s_axi_gp0
 
remoteport_tlm_memory_slave rp_s_axi_gp1
 
remoteport_tlm_memory_slave rp_s_axi_hp0
 
remoteport_tlm_memory_slave rp_s_axi_hp1
 
remoteport_tlm_memory_slave rp_s_axi_hp2
 
remoteport_tlm_memory_slave rp_s_axi_hp3
 
remoteport_tlm_memory_slave rp_s_axi_acp
 
remoteport_tlm_wires rp_wires_in
 
remoteport_tlm_wires rp_wires_out
 
remoteport_tlm_wires rp_irq_out
 

Detailed Description

Definition at line 39 of file xilinx-zynq.h.

Constructor & Destructor Documentation

◆ xilinx_zynq()

xilinx_zynq::xilinx_zynq ( sc_core::sc_module_name  name,
const char *  sk_descr 
)

Member Data Documentation

◆ m_axi_gp

tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master>* xilinx_zynq::m_axi_gp[2]

◆ pl2ps_irq

sc_vector<sc_signal<bool> > xilinx_zynq::pl2ps_irq

Definition at line 93 of file xilinx-zynq.h.

Referenced by processing_system7_v5_5_tlm::IRQ_F2P_method().

◆ ps2pl_irq

sc_vector<sc_signal<bool> > xilinx_zynq::ps2pl_irq

Definition at line 96 of file xilinx-zynq.h.

◆ ps2pl_rst

sc_vector<sc_signal<bool> > xilinx_zynq::ps2pl_rst

Definition at line 99 of file xilinx-zynq.h.

Referenced by processing_system7_v5_5_tlm::FCLK_RESET0_N_trigger().

◆ rp_irq_out

remoteport_tlm_wires xilinx_zynq::rp_irq_out
private

Definition at line 58 of file xilinx-zynq.h.

◆ rp_m_axi_gp0

remoteport_tlm_memory_master xilinx_zynq::rp_m_axi_gp0
private

Definition at line 43 of file xilinx-zynq.h.

◆ rp_m_axi_gp1

remoteport_tlm_memory_master xilinx_zynq::rp_m_axi_gp1
private

Definition at line 44 of file xilinx-zynq.h.

◆ rp_s_axi_acp

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_acp
private

Definition at line 54 of file xilinx-zynq.h.

◆ rp_s_axi_gp0

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_gp0
private

Definition at line 46 of file xilinx-zynq.h.

◆ rp_s_axi_gp1

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_gp1
private

Definition at line 47 of file xilinx-zynq.h.

◆ rp_s_axi_hp0

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_hp0
private

Definition at line 49 of file xilinx-zynq.h.

◆ rp_s_axi_hp1

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_hp1
private

Definition at line 50 of file xilinx-zynq.h.

◆ rp_s_axi_hp2

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_hp2
private

Definition at line 51 of file xilinx-zynq.h.

◆ rp_s_axi_hp3

remoteport_tlm_memory_slave xilinx_zynq::rp_s_axi_hp3
private

Definition at line 52 of file xilinx-zynq.h.

◆ rp_wires_in

remoteport_tlm_wires xilinx_zynq::rp_wires_in
private

Definition at line 56 of file xilinx-zynq.h.

◆ rp_wires_out

remoteport_tlm_wires xilinx_zynq::rp_wires_out
private

Definition at line 57 of file xilinx-zynq.h.

◆ s_axi_acp

tlm_utils::simple_target_socket<remoteport_tlm_memory_slave>* xilinx_zynq::s_axi_acp

Definition at line 90 of file xilinx-zynq.h.

◆ s_axi_gp

tlm_utils::simple_target_socket<remoteport_tlm_memory_slave>* xilinx_zynq::s_axi_gp[2]

Definition at line 88 of file xilinx-zynq.h.

◆ s_axi_hp

tlm_utils::simple_target_socket<remoteport_tlm_memory_slave>* xilinx_zynq::s_axi_hp[4]

The documentation for this class was generated from the following file: