SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
synth_1/dont_touch.xdc
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1 # This file is automatically generated.
2 # It contains project source information necessary for synthesis and implementation.
3 
4 # XDC: /home/david/Documents/GitHub/SimpleVOut/djrm_bd/system.xdc
5 
6 # XDC: /home/david/Documents/GitHub/djrm-EBAZ4205/board/sources/ebaz4205.xdc
7 
8 # Block Designs: bd/design_1/design_1.bd
9 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1 || ORIG_REF_NAME==design_1} -quiet] -quiet
10 
11 # IP: bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
12 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_processing_system7_0_0 || ORIG_REF_NAME==design_1_processing_system7_0_0} -quiet] -quiet
13 
14 # IP: bd/design_1/ip/design_1_xlconcat_0_0/design_1_xlconcat_0_0.xci
15 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_xlconcat_0_0 || ORIG_REF_NAME==design_1_xlconcat_0_0} -quiet] -quiet
16 
17 # IP: bd/design_1/ip/design_1_xlconstant_0_0/design_1_xlconstant_0_0.xci
18 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_xlconstant_0_0 || ORIG_REF_NAME==design_1_xlconstant_0_0} -quiet] -quiet
19 
20 # IP: bd/design_1/ip/design_1_xlslice_0_0/design_1_xlslice_0_0.xci
21 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_xlslice_0_0 || ORIG_REF_NAME==design_1_xlslice_0_0} -quiet] -quiet
22 
23 # IP: bd/design_1/ip/design_1_framebuffer_0/design_1_framebuffer_0.xci
24 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_framebuffer_0 || ORIG_REF_NAME==design_1_framebuffer_0} -quiet] -quiet
25 
26 # IP: bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0.xci
27 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_clk_wiz_0 || ORIG_REF_NAME==design_1_clk_wiz_0} -quiet] -quiet
28 
29 # IP: bd/design_1/ip/design_1_axi_mem_intercon_0/design_1_axi_mem_intercon_0.xci
30 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_axi_mem_intercon_0 || ORIG_REF_NAME==design_1_axi_mem_intercon_0} -quiet] -quiet
31 
32 # IP: bd/design_1/ip/design_1_rst_ps7_0_125M_0/design_1_rst_ps7_0_125M_0.xci
33 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_rst_ps7_0_125M_0 || ORIG_REF_NAME==design_1_rst_ps7_0_125M_0} -quiet] -quiet
34 
35 # IP: bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci
36 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_xbar_0 || ORIG_REF_NAME==design_1_xbar_0} -quiet] -quiet
37 
38 # IP: bd/design_1/ip/design_1_ps7_0_axi_periph_0/design_1_ps7_0_axi_periph_0.xci
39 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_ps7_0_axi_periph_0 || ORIG_REF_NAME==design_1_ps7_0_axi_periph_0} -quiet] -quiet
40 
41 # IP: bd/design_1/ip/design_1_axi_uartlite_0_0/design_1_axi_uartlite_0_0.xci
42 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_axi_uartlite_0_0 || ORIG_REF_NAME==design_1_axi_uartlite_0_0} -quiet] -quiet
43 
44 # IP: bd/design_1/ip/design_1_axi_ps2_0_0/design_1_axi_ps2_0_0.xci
45 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_axi_ps2_0_0 || ORIG_REF_NAME==design_1_axi_ps2_0_0} -quiet] -quiet
46 
47 # IP: bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci
48 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_auto_pc_0 || ORIG_REF_NAME==design_1_auto_pc_0} -quiet] -quiet
49 
50 # IP: bd/design_1/ip/design_1_auto_pc_1/design_1_auto_pc_1.xci
51 set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==design_1_auto_pc_1 || ORIG_REF_NAME==design_1_auto_pc_1} -quiet] -quiet
52 
53 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc