SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_processing_system7_0_0_synth_1/dont_touch.xdc
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1 # This file is automatically generated.
2 # It contains project source information necessary for synthesis and implementation.
3 
4 # IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
5 # IP: The module: 'design_1_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
6 
7 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc
8 # XDC: The top module name and the constraint reference have the same name: 'design_1_processing_system7_0_0'. Do not add the DONT_TOUCH constraint.
9 set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
10 
11 # IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
12 # IP: The module: 'design_1_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
13 
14 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc
15 # XDC: The top module name and the constraint reference have the same name: 'design_1_processing_system7_0_0'. Do not add the DONT_TOUCH constraint.
16 #dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet