SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_processing_system7_0_0.xdc
Go to the documentation of this file.
1 ############################################################################
2 ##
3 ## Xilinx, Inc. 2006 www.xilinx.com
4 ############################################################################
5 ## File name : ps7_constraints.xdc
6 ##
7 ## Details : Constraints file
8 ## FPGA family: zynq
9 ## FPGA: xc7z010clg400-1
10 ## Device Size: xc7z010
11 ## Package: clg400
12 ## Speedgrade: -1
13 ##
14 ##
15 ############################################################################
16 ############################################################################
17 ############################################################################
18 # Clock constraints #
19 ############################################################################
20 create_clock -name clk_fpga_1 -period "40" [get_pins "PS7_i/FCLKCLK[1]"]
21 set_input_jitter clk_fpga_1 1.2
22 #The clocks are asynchronous, user should constrain them appropriately.#
23 create_clock -name clk_fpga_3 -period "10" [get_pins "PS7_i/FCLKCLK[3]"]
24 set_input_jitter clk_fpga_3 0.3
25 #The clocks are asynchronous, user should constrain them appropriately.#
26 create_clock -name clk_fpga_2 -period "29.999" [get_pins "PS7_i/FCLKCLK[2]"]
27 set_input_jitter clk_fpga_2 0.89997
28 #The clocks are asynchronous, user should constrain them appropriately.#
29 create_clock -name clk_fpga_0 -period "8" [get_pins "PS7_i/FCLKCLK[0]"]
30 set_input_jitter clk_fpga_0 0.24
31 #The clocks are asynchronous, user should constrain them appropriately.#
32 
33 
34 ############################################################################
35 # I/O STANDARDS and Location Constraints #
36 ############################################################################
37 
38 # GPIO / gpio[53] / MIO[53]
39 set_property iostandard "LVCMOS33" [get_ports "MIO[53]"]
40 set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
41 set_property slew "slow" [get_ports "MIO[53]"]
42 set_property drive "8" [get_ports "MIO[53]"]
43 set_property pullup "TRUE" [get_ports "MIO[53]"]
44 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
45 # GPIO / gpio[52] / MIO[52]
46 set_property iostandard "LVCMOS33" [get_ports "MIO[52]"]
47 set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
48 set_property slew "slow" [get_ports "MIO[52]"]
49 set_property drive "8" [get_ports "MIO[52]"]
50 set_property pullup "TRUE" [get_ports "MIO[52]"]
51 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[52]"]
52 # GPIO / gpio[51] / MIO[51]
53 set_property iostandard "LVCMOS33" [get_ports "MIO[51]"]
54 set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
55 set_property slew "slow" [get_ports "MIO[51]"]
56 set_property drive "8" [get_ports "MIO[51]"]
57 set_property pullup "TRUE" [get_ports "MIO[51]"]
58 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
59 # GPIO / gpio[50] / MIO[50]
60 set_property iostandard "LVCMOS33" [get_ports "MIO[50]"]
61 set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
62 set_property slew "slow" [get_ports "MIO[50]"]
63 set_property drive "8" [get_ports "MIO[50]"]
64 set_property pullup "TRUE" [get_ports "MIO[50]"]
65 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
66 # GPIO / gpio[49] / MIO[49]
67 set_property iostandard "LVCMOS33" [get_ports "MIO[49]"]
68 set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
69 set_property slew "slow" [get_ports "MIO[49]"]
70 set_property drive "8" [get_ports "MIO[49]"]
71 set_property pullup "TRUE" [get_ports "MIO[49]"]
72 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[49]"]
73 # GPIO / gpio[48] / MIO[48]
74 set_property iostandard "LVCMOS33" [get_ports "MIO[48]"]
75 set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
76 set_property slew "slow" [get_ports "MIO[48]"]
77 set_property drive "8" [get_ports "MIO[48]"]
78 set_property pullup "TRUE" [get_ports "MIO[48]"]
79 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[48]"]
80 # GPIO / gpio[47] / MIO[47]
81 set_property iostandard "LVCMOS33" [get_ports "MIO[47]"]
82 set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
83 set_property slew "slow" [get_ports "MIO[47]"]
84 set_property drive "8" [get_ports "MIO[47]"]
85 set_property pullup "TRUE" [get_ports "MIO[47]"]
86 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[47]"]
87 # GPIO / gpio[46] / MIO[46]
88 set_property iostandard "LVCMOS33" [get_ports "MIO[46]"]
89 set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
90 set_property slew "slow" [get_ports "MIO[46]"]
91 set_property drive "8" [get_ports "MIO[46]"]
92 set_property pullup "TRUE" [get_ports "MIO[46]"]
93 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"]
94 # SD 0 / data[3] / MIO[45]
95 set_property iostandard "LVCMOS33" [get_ports "MIO[45]"]
96 set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
97 set_property slew "slow" [get_ports "MIO[45]"]
98 set_property drive "8" [get_ports "MIO[45]"]
99 set_property pullup "TRUE" [get_ports "MIO[45]"]
100 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
101 # SD 0 / data[2] / MIO[44]
102 set_property iostandard "LVCMOS33" [get_ports "MIO[44]"]
103 set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
104 set_property slew "slow" [get_ports "MIO[44]"]
105 set_property drive "8" [get_ports "MIO[44]"]
106 set_property pullup "TRUE" [get_ports "MIO[44]"]
107 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
108 # SD 0 / data[1] / MIO[43]
109 set_property iostandard "LVCMOS33" [get_ports "MIO[43]"]
110 set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
111 set_property slew "slow" [get_ports "MIO[43]"]
112 set_property drive "8" [get_ports "MIO[43]"]
113 set_property pullup "TRUE" [get_ports "MIO[43]"]
114 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
115 # SD 0 / data[0] / MIO[42]
116 set_property iostandard "LVCMOS33" [get_ports "MIO[42]"]
117 set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
118 set_property slew "slow" [get_ports "MIO[42]"]
119 set_property drive "8" [get_ports "MIO[42]"]
120 set_property pullup "TRUE" [get_ports "MIO[42]"]
121 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
122 # SD 0 / cmd / MIO[41]
123 set_property iostandard "LVCMOS33" [get_ports "MIO[41]"]
124 set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
125 set_property slew "slow" [get_ports "MIO[41]"]
126 set_property drive "8" [get_ports "MIO[41]"]
127 set_property pullup "TRUE" [get_ports "MIO[41]"]
128 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
129 # SD 0 / clk / MIO[40]
130 set_property iostandard "LVCMOS33" [get_ports "MIO[40]"]
131 set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
132 set_property slew "slow" [get_ports "MIO[40]"]
133 set_property drive "8" [get_ports "MIO[40]"]
134 set_property pullup "TRUE" [get_ports "MIO[40]"]
135 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
136 # GPIO / gpio[39] / MIO[39]
137 set_property iostandard "LVCMOS33" [get_ports "MIO[39]"]
138 set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
139 set_property slew "slow" [get_ports "MIO[39]"]
140 set_property drive "8" [get_ports "MIO[39]"]
141 set_property pullup "TRUE" [get_ports "MIO[39]"]
142 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
143 # GPIO / gpio[38] / MIO[38]
144 set_property iostandard "LVCMOS33" [get_ports "MIO[38]"]
145 set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
146 set_property slew "slow" [get_ports "MIO[38]"]
147 set_property drive "8" [get_ports "MIO[38]"]
148 set_property pullup "TRUE" [get_ports "MIO[38]"]
149 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
150 # GPIO / gpio[37] / MIO[37]
151 set_property iostandard "LVCMOS33" [get_ports "MIO[37]"]
152 set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
153 set_property slew "slow" [get_ports "MIO[37]"]
154 set_property drive "8" [get_ports "MIO[37]"]
155 set_property pullup "TRUE" [get_ports "MIO[37]"]
156 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
157 # GPIO / gpio[36] / MIO[36]
158 set_property iostandard "LVCMOS33" [get_ports "MIO[36]"]
159 set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
160 set_property slew "slow" [get_ports "MIO[36]"]
161 set_property drive "8" [get_ports "MIO[36]"]
162 set_property pullup "TRUE" [get_ports "MIO[36]"]
163 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[36]"]
164 # GPIO / gpio[35] / MIO[35]
165 set_property iostandard "LVCMOS33" [get_ports "MIO[35]"]
166 set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
167 set_property slew "slow" [get_ports "MIO[35]"]
168 set_property drive "8" [get_ports "MIO[35]"]
169 set_property pullup "TRUE" [get_ports "MIO[35]"]
170 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
171 # GPIO / gpio[34] / MIO[34]
172 set_property iostandard "LVCMOS33" [get_ports "MIO[34]"]
173 set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
174 set_property slew "slow" [get_ports "MIO[34]"]
175 set_property drive "8" [get_ports "MIO[34]"]
176 set_property pullup "TRUE" [get_ports "MIO[34]"]
177 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
178 # GPIO / gpio[33] / MIO[33]
179 set_property iostandard "LVCMOS33" [get_ports "MIO[33]"]
180 set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
181 set_property slew "slow" [get_ports "MIO[33]"]
182 set_property drive "8" [get_ports "MIO[33]"]
183 set_property pullup "TRUE" [get_ports "MIO[33]"]
184 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
185 # GPIO / gpio[32] / MIO[32]
186 set_property iostandard "LVCMOS33" [get_ports "MIO[32]"]
187 set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
188 set_property slew "slow" [get_ports "MIO[32]"]
189 set_property drive "8" [get_ports "MIO[32]"]
190 set_property pullup "TRUE" [get_ports "MIO[32]"]
191 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
192 # GPIO / gpio[31] / MIO[31]
193 set_property iostandard "LVCMOS33" [get_ports "MIO[31]"]
194 set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
195 set_property slew "slow" [get_ports "MIO[31]"]
196 set_property drive "8" [get_ports "MIO[31]"]
197 set_property pullup "TRUE" [get_ports "MIO[31]"]
198 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"]
199 # GPIO / gpio[30] / MIO[30]
200 set_property iostandard "LVCMOS33" [get_ports "MIO[30]"]
201 set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
202 set_property slew "slow" [get_ports "MIO[30]"]
203 set_property drive "8" [get_ports "MIO[30]"]
204 set_property pullup "TRUE" [get_ports "MIO[30]"]
205 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"]
206 # GPIO / gpio[29] / MIO[29]
207 set_property iostandard "LVCMOS33" [get_ports "MIO[29]"]
208 set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
209 set_property slew "slow" [get_ports "MIO[29]"]
210 set_property drive "8" [get_ports "MIO[29]"]
211 set_property pullup "TRUE" [get_ports "MIO[29]"]
212 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"]
213 # GPIO / gpio[28] / MIO[28]
214 set_property iostandard "LVCMOS33" [get_ports "MIO[28]"]
215 set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
216 set_property slew "slow" [get_ports "MIO[28]"]
217 set_property drive "8" [get_ports "MIO[28]"]
218 set_property pullup "TRUE" [get_ports "MIO[28]"]
219 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
220 # I2C 0 / sda / MIO[27]
221 set_property iostandard "LVCMOS33" [get_ports "MIO[27]"]
222 set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
223 set_property slew "slow" [get_ports "MIO[27]"]
224 set_property drive "8" [get_ports "MIO[27]"]
225 set_property pullup "TRUE" [get_ports "MIO[27]"]
226 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[27]"]
227 # I2C 0 / scl / MIO[26]
228 set_property iostandard "LVCMOS33" [get_ports "MIO[26]"]
229 set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
230 set_property slew "slow" [get_ports "MIO[26]"]
231 set_property drive "8" [get_ports "MIO[26]"]
232 set_property pullup "TRUE" [get_ports "MIO[26]"]
233 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[26]"]
234 # UART 1 / rx / MIO[25]
235 set_property iostandard "LVCMOS33" [get_ports "MIO[25]"]
236 set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
237 set_property slew "slow" [get_ports "MIO[25]"]
238 set_property drive "8" [get_ports "MIO[25]"]
239 set_property pullup "TRUE" [get_ports "MIO[25]"]
240 set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
241 # UART 1 / tx / MIO[24]
242 set_property iostandard "LVCMOS33" [get_ports "MIO[24]"]
243 set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
244 set_property slew "slow" [get_ports "MIO[24]"]
245 set_property drive "8" [get_ports "MIO[24]"]
246 set_property pullup "TRUE" [get_ports "MIO[24]"]
247 set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[24]"]
248 # GPIO / gpio[23] / MIO[23]
249 set_property iostandard "LVCMOS33" [get_ports "MIO[23]"]
250 set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
251 set_property slew "slow" [get_ports "MIO[23]"]
252 set_property drive "8" [get_ports "MIO[23]"]
253 set_property pullup "TRUE" [get_ports "MIO[23]"]
254 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[23]"]
255 # GPIO / gpio[22] / MIO[22]
256 set_property iostandard "LVCMOS33" [get_ports "MIO[22]"]
257 set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
258 set_property slew "slow" [get_ports "MIO[22]"]
259 set_property drive "8" [get_ports "MIO[22]"]
260 set_property pullup "TRUE" [get_ports "MIO[22]"]
261 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[22]"]
262 # GPIO / gpio[21] / MIO[21]
263 set_property iostandard "LVCMOS33" [get_ports "MIO[21]"]
264 set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
265 set_property slew "slow" [get_ports "MIO[21]"]
266 set_property drive "8" [get_ports "MIO[21]"]
267 set_property pullup "TRUE" [get_ports "MIO[21]"]
268 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"]
269 # GPIO / gpio[20] / MIO[20]
270 set_property iostandard "LVCMOS33" [get_ports "MIO[20]"]
271 set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
272 set_property slew "slow" [get_ports "MIO[20]"]
273 set_property drive "8" [get_ports "MIO[20]"]
274 set_property pullup "TRUE" [get_ports "MIO[20]"]
275 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[20]"]
276 # GPIO / gpio[19] / MIO[19]
277 set_property iostandard "LVCMOS33" [get_ports "MIO[19]"]
278 set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
279 set_property slew "slow" [get_ports "MIO[19]"]
280 set_property drive "8" [get_ports "MIO[19]"]
281 set_property pullup "TRUE" [get_ports "MIO[19]"]
282 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[19]"]
283 # GPIO / gpio[18] / MIO[18]
284 set_property iostandard "LVCMOS33" [get_ports "MIO[18]"]
285 set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
286 set_property slew "slow" [get_ports "MIO[18]"]
287 set_property drive "8" [get_ports "MIO[18]"]
288 set_property pullup "TRUE" [get_ports "MIO[18]"]
289 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[18]"]
290 # GPIO / gpio[17] / MIO[17]
291 set_property iostandard "LVCMOS33" [get_ports "MIO[17]"]
292 set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
293 set_property slew "slow" [get_ports "MIO[17]"]
294 set_property drive "8" [get_ports "MIO[17]"]
295 set_property pullup "TRUE" [get_ports "MIO[17]"]
296 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[17]"]
297 # GPIO / gpio[16] / MIO[16]
298 set_property iostandard "LVCMOS33" [get_ports "MIO[16]"]
299 set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
300 set_property slew "slow" [get_ports "MIO[16]"]
301 set_property drive "8" [get_ports "MIO[16]"]
302 set_property pullup "TRUE" [get_ports "MIO[16]"]
303 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"]
304 # GPIO / gpio[15] / MIO[15]
305 set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
306 set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
307 set_property slew "slow" [get_ports "MIO[15]"]
308 set_property drive "8" [get_ports "MIO[15]"]
309 set_property pullup "TRUE" [get_ports "MIO[15]"]
310 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
311 # NAND Flash / busy / MIO[14]
312 set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
313 set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
314 set_property slew "slow" [get_ports "MIO[14]"]
315 set_property drive "8" [get_ports "MIO[14]"]
316 set_property pullup "TRUE" [get_ports "MIO[14]"]
317 set_property PIO_DIRECTION "INPUT" [get_ports "MIO[14]"]
318 # NAND Flash / data[3] / MIO[13]
319 set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
320 set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
321 set_property slew "slow" [get_ports "MIO[13]"]
322 set_property drive "8" [get_ports "MIO[13]"]
323 set_property pullup "TRUE" [get_ports "MIO[13]"]
324 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
325 # NAND Flash / data[7] / MIO[12]
326 set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
327 set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
328 set_property slew "slow" [get_ports "MIO[12]"]
329 set_property drive "8" [get_ports "MIO[12]"]
330 set_property pullup "TRUE" [get_ports "MIO[12]"]
331 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
332 # NAND Flash / data[6] / MIO[11]
333 set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
334 set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
335 set_property slew "slow" [get_ports "MIO[11]"]
336 set_property drive "8" [get_ports "MIO[11]"]
337 set_property pullup "TRUE" [get_ports "MIO[11]"]
338 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
339 # NAND Flash / data[5] / MIO[10]
340 set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
341 set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
342 set_property slew "slow" [get_ports "MIO[10]"]
343 set_property drive "8" [get_ports "MIO[10]"]
344 set_property pullup "TRUE" [get_ports "MIO[10]"]
345 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
346 # NAND Flash / data[4] / MIO[9]
347 set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
348 set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
349 set_property slew "slow" [get_ports "MIO[9]"]
350 set_property drive "8" [get_ports "MIO[9]"]
351 set_property pullup "TRUE" [get_ports "MIO[9]"]
352 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
353 # NAND Flash / re_b / MIO[8]
354 set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
355 set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
356 set_property slew "slow" [get_ports "MIO[8]"]
357 set_property drive "8" [get_ports "MIO[8]"]
358 set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
359 # NAND Flash / cle / MIO[7]
360 set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
361 set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
362 set_property slew "slow" [get_ports "MIO[7]"]
363 set_property drive "8" [get_ports "MIO[7]"]
364 set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
365 # NAND Flash / data[1] / MIO[6]
366 set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
367 set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
368 set_property slew "slow" [get_ports "MIO[6]"]
369 set_property drive "8" [get_ports "MIO[6]"]
370 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[6]"]
371 # NAND Flash / data[0] / MIO[5]
372 set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
373 set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
374 set_property slew "slow" [get_ports "MIO[5]"]
375 set_property drive "8" [get_ports "MIO[5]"]
376 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
377 # NAND Flash / data[2] / MIO[4]
378 set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
379 set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
380 set_property slew "slow" [get_ports "MIO[4]"]
381 set_property drive "8" [get_ports "MIO[4]"]
382 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
383 # NAND Flash / we_b / MIO[3]
384 set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
385 set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
386 set_property slew "slow" [get_ports "MIO[3]"]
387 set_property drive "8" [get_ports "MIO[3]"]
388 set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[3]"]
389 # NAND Flash / ale / MIO[2]
390 set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
391 set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
392 set_property slew "slow" [get_ports "MIO[2]"]
393 set_property drive "8" [get_ports "MIO[2]"]
394 set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[2]"]
395 # GPIO / gpio[1] / MIO[1]
396 set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
397 set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
398 set_property slew "slow" [get_ports "MIO[1]"]
399 set_property drive "8" [get_ports "MIO[1]"]
400 set_property pullup "TRUE" [get_ports "MIO[1]"]
401 set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[1]"]
402 # NAND Flash / cs / MIO[0]
403 set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
404 set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
405 set_property slew "slow" [get_ports "MIO[0]"]
406 set_property drive "8" [get_ports "MIO[0]"]
407 set_property pullup "TRUE" [get_ports "MIO[0]"]
408 set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[0]"]
409 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"]
410 set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
411 set_property slew "FAST" [get_ports "DDR_VRP"]
412 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
413 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"]
414 set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
415 set_property slew "FAST" [get_ports "DDR_VRN"]
416 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
417 set_property iostandard "SSTL135" [get_ports "DDR_WEB"]
418 set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
419 set_property slew "SLOW" [get_ports "DDR_WEB"]
420 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
421 set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"]
422 set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
423 set_property slew "SLOW" [get_ports "DDR_RAS_n"]
424 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
425 set_property iostandard "SSTL135" [get_ports "DDR_ODT"]
426 set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
427 set_property slew "SLOW" [get_ports "DDR_ODT"]
428 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
429 set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"]
430 set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
431 set_property slew "FAST" [get_ports "DDR_DRSTB"]
432 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
433 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"]
434 set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
435 set_property slew "FAST" [get_ports "DDR_DQS[3]"]
436 set_property pullup "TRUE" [get_ports "DDR_DQS[3]"]
437 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
438 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"]
439 set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
440 set_property slew "FAST" [get_ports "DDR_DQS[2]"]
441 set_property pullup "TRUE" [get_ports "DDR_DQS[2]"]
442 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
443 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"]
444 set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
445 set_property slew "FAST" [get_ports "DDR_DQS[1]"]
446 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
447 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"]
448 set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
449 set_property slew "FAST" [get_ports "DDR_DQS[0]"]
450 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
451 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"]
452 set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
453 set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
454 set_property pullup "TRUE" [get_ports "DDR_DQS_n[3]"]
455 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
456 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"]
457 set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
458 set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
459 set_property pullup "TRUE" [get_ports "DDR_DQS_n[2]"]
460 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
461 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"]
462 set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
463 set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
464 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
465 set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"]
466 set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
467 set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
468 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
469 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"]
470 set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
471 set_property slew "FAST" [get_ports "DDR_DQ[9]"]
472 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
473 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"]
474 set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
475 set_property slew "FAST" [get_ports "DDR_DQ[8]"]
476 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
477 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"]
478 set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
479 set_property slew "FAST" [get_ports "DDR_DQ[7]"]
480 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
481 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"]
482 set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
483 set_property slew "FAST" [get_ports "DDR_DQ[6]"]
484 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
485 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"]
486 set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
487 set_property slew "FAST" [get_ports "DDR_DQ[5]"]
488 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
489 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"]
490 set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
491 set_property slew "FAST" [get_ports "DDR_DQ[4]"]
492 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
493 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"]
494 set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
495 set_property slew "FAST" [get_ports "DDR_DQ[3]"]
496 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
497 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"]
498 set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
499 set_property slew "FAST" [get_ports "DDR_DQ[31]"]
500 set_property pullup "TRUE" [get_ports "DDR_DQ[31]"]
501 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
502 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"]
503 set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
504 set_property slew "FAST" [get_ports "DDR_DQ[30]"]
505 set_property pullup "TRUE" [get_ports "DDR_DQ[30]"]
506 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
507 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"]
508 set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
509 set_property slew "FAST" [get_ports "DDR_DQ[2]"]
510 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
511 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"]
512 set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
513 set_property slew "FAST" [get_ports "DDR_DQ[29]"]
514 set_property pullup "TRUE" [get_ports "DDR_DQ[29]"]
515 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
516 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"]
517 set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
518 set_property slew "FAST" [get_ports "DDR_DQ[28]"]
519 set_property pullup "TRUE" [get_ports "DDR_DQ[28]"]
520 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
521 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"]
522 set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
523 set_property slew "FAST" [get_ports "DDR_DQ[27]"]
524 set_property pullup "TRUE" [get_ports "DDR_DQ[27]"]
525 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
526 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"]
527 set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
528 set_property slew "FAST" [get_ports "DDR_DQ[26]"]
529 set_property pullup "TRUE" [get_ports "DDR_DQ[26]"]
530 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
531 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"]
532 set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
533 set_property slew "FAST" [get_ports "DDR_DQ[25]"]
534 set_property pullup "TRUE" [get_ports "DDR_DQ[25]"]
535 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
536 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"]
537 set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
538 set_property slew "FAST" [get_ports "DDR_DQ[24]"]
539 set_property pullup "TRUE" [get_ports "DDR_DQ[24]"]
540 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
541 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"]
542 set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
543 set_property slew "FAST" [get_ports "DDR_DQ[23]"]
544 set_property pullup "TRUE" [get_ports "DDR_DQ[23]"]
545 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
546 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"]
547 set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
548 set_property slew "FAST" [get_ports "DDR_DQ[22]"]
549 set_property pullup "TRUE" [get_ports "DDR_DQ[22]"]
550 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
551 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"]
552 set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
553 set_property slew "FAST" [get_ports "DDR_DQ[21]"]
554 set_property pullup "TRUE" [get_ports "DDR_DQ[21]"]
555 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
556 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"]
557 set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
558 set_property slew "FAST" [get_ports "DDR_DQ[20]"]
559 set_property pullup "TRUE" [get_ports "DDR_DQ[20]"]
560 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
561 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"]
562 set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
563 set_property slew "FAST" [get_ports "DDR_DQ[1]"]
564 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
565 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"]
566 set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
567 set_property slew "FAST" [get_ports "DDR_DQ[19]"]
568 set_property pullup "TRUE" [get_ports "DDR_DQ[19]"]
569 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
570 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"]
571 set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
572 set_property slew "FAST" [get_ports "DDR_DQ[18]"]
573 set_property pullup "TRUE" [get_ports "DDR_DQ[18]"]
574 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
575 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"]
576 set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
577 set_property slew "FAST" [get_ports "DDR_DQ[17]"]
578 set_property pullup "TRUE" [get_ports "DDR_DQ[17]"]
579 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
580 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"]
581 set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
582 set_property slew "FAST" [get_ports "DDR_DQ[16]"]
583 set_property pullup "TRUE" [get_ports "DDR_DQ[16]"]
584 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
585 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"]
586 set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
587 set_property slew "FAST" [get_ports "DDR_DQ[15]"]
588 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
589 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"]
590 set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
591 set_property slew "FAST" [get_ports "DDR_DQ[14]"]
592 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
593 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"]
594 set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
595 set_property slew "FAST" [get_ports "DDR_DQ[13]"]
596 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
597 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"]
598 set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
599 set_property slew "FAST" [get_ports "DDR_DQ[12]"]
600 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
601 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"]
602 set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
603 set_property slew "FAST" [get_ports "DDR_DQ[11]"]
604 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
605 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"]
606 set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
607 set_property slew "FAST" [get_ports "DDR_DQ[10]"]
608 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
609 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"]
610 set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
611 set_property slew "FAST" [get_ports "DDR_DQ[0]"]
612 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
613 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"]
614 set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
615 set_property slew "FAST" [get_ports "DDR_DM[3]"]
616 set_property pullup "TRUE" [get_ports "DDR_DM[3]"]
617 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
618 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"]
619 set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
620 set_property slew "FAST" [get_ports "DDR_DM[2]"]
621 set_property pullup "TRUE" [get_ports "DDR_DM[2]"]
622 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
623 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"]
624 set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
625 set_property slew "FAST" [get_ports "DDR_DM[1]"]
626 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
627 set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"]
628 set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
629 set_property slew "FAST" [get_ports "DDR_DM[0]"]
630 set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
631 set_property iostandard "SSTL135" [get_ports "DDR_CS_n"]
632 set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
633 set_property slew "SLOW" [get_ports "DDR_CS_n"]
634 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
635 set_property iostandard "SSTL135" [get_ports "DDR_CKE"]
636 set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
637 set_property slew "SLOW" [get_ports "DDR_CKE"]
638 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
639 set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"]
640 set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
641 set_property slew "FAST" [get_ports "DDR_Clk"]
642 set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
643 set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"]
644 set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
645 set_property slew "FAST" [get_ports "DDR_Clk_n"]
646 set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
647 set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"]
648 set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
649 set_property slew "SLOW" [get_ports "DDR_CAS_n"]
650 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
651 set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"]
652 set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
653 set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
654 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
655 set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"]
656 set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
657 set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
658 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
659 set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"]
660 set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
661 set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
662 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
663 set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"]
664 set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
665 set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
666 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
667 set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"]
668 set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
669 set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
670 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
671 set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"]
672 set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
673 set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
674 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
675 set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"]
676 set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
677 set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
678 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
679 set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"]
680 set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
681 set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
682 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
683 set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"]
684 set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
685 set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
686 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
687 set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"]
688 set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
689 set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
690 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
691 set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"]
692 set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
693 set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
694 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
695 set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"]
696 set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
697 set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
698 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
699 set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"]
700 set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
701 set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
702 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
703 set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"]
704 set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
705 set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
706 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
707 set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"]
708 set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
709 set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
710 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
711 set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"]
712 set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
713 set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
714 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
715 set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"]
716 set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
717 set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
718 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
719 set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"]
720 set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
721 set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
722 set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
723 set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
724 set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
725 set_property slew "fast" [get_ports "PS_PORB"]
726 set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"]
727 set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
728 set_property slew "fast" [get_ports "PS_SRSTB"]
729 set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
730 set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
731 set_property slew "fast" [get_ports "PS_CLK"]
732