SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_ooc.xdc
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2 
3 # This XDC is used only for OOC mode of synthesis, implementation
4 # This constraints file contains default clock frequencies to be used during
5 # out-of-context flows such as OOC Synthesis and Hierarchical Designs.
6 # This constraints file is not used in normal top-down synthesis (default flow
7 # of Vivado)
8 ################################################################################
9 create_clock -name ENET0_GMII_RX_CLK_0 -period 10 [get_ports ENET0_GMII_RX_CLK_0]
10 create_clock -name ENET0_GMII_TX_CLK_0 -period 10 [get_ports ENET0_GMII_TX_CLK_0]
11 create_clock -name processing_system7_0_FCLK_CLK0 -period 8 [get_pins processing_system7_0/FCLK_CLK0]
12 create_clock -name processing_system7_0_FCLK_CLK1 -period 40 [get_pins processing_system7_0/FCLK_CLK1]
13 create_clock -name processing_system7_0_FCLK_CLK2 -period 30 [get_pins processing_system7_0/FCLK_CLK2]
14 create_clock -name processing_system7_0_FCLK_CLK3 -period 10 [get_pins processing_system7_0/FCLK_CLK3]
15 
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