SimpleVOut  1.0.0 Initial
A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
design_1_clk_wiz_0_synth_1/dont_touch.xdc
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1 # This file is automatically generated.
2 # It contains project source information necessary for synthesis and implementation.
3 
4 # IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0.xci
5 # IP: The module: 'design_1_clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
6 
7 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_board.xdc
8 # XDC: The top module name and the constraint reference have the same name: 'design_1_clk_wiz_0'. Do not add the DONT_TOUCH constraint.
9 set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
10 
11 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0.xdc
12 # XDC: The top module name and the constraint reference have the same name: 'design_1_clk_wiz_0'. Do not add the DONT_TOUCH constraint.
13 #dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
14 
15 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_ooc.xdc
16 # XDC: The top module name and the constraint reference have the same name: 'design_1_clk_wiz_0'. Do not add the DONT_TOUCH constraint.
17 #dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
18 
19 # IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0.xci
20 # IP: The module: 'design_1_clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
21 
22 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_board.xdc
23 # XDC: The top module name and the constraint reference have the same name: 'design_1_clk_wiz_0'. Do not add the DONT_TOUCH constraint.
24 #dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
25 
26 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0.xdc
27 # XDC: The top module name and the constraint reference have the same name: 'design_1_clk_wiz_0'. Do not add the DONT_TOUCH constraint.
28 #dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
29 
30 # XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_ooc.xdc
31 # XDC: The top module name and the constraint reference have the same name: 'design_1_clk_wiz_0'. Do not add the DONT_TOUCH constraint.
32 #dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet