design_1_axi_ps2_0_0_synth_1/dont_touch.xdc

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# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
 
# IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ps2_0_0/design_1_axi_ps2_0_0.xci
# IP: The module: 'design_1_axi_ps2_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
 
# IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_axi_ps2_0_0/src/fifo_generator_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==fifo_generator_0 || ORIG_REF_NAME==fifo_generator_0} -quiet] -quiet
 
# XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_axi_ps2_0_0/src/fifo_generator_0.xdc
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==fifo_generator_0 || ORIG_REF_NAME==fifo_generator_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
 
# IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_ps2_0_0/design_1_axi_ps2_0_0.xci
# IP: The module: 'design_1_axi_ps2_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
 
# IP: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_axi_ps2_0_0/src/fifo_generator_0.xci
#dup# set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==fifo_generator_0 || ORIG_REF_NAME==fifo_generator_0} -quiet] -quiet
 
# XDC: /home/david/Documents/GitHub/SimpleVOut/Demos/myproj/project_1.gen/sources_1/bd/design_1/ip/design_1_axi_ps2_0_0/src/fifo_generator_0.xdc
#dup# set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==fifo_generator_0 || ORIG_REF_NAME==fifo_generator_0} -quiet] {/U0 } ]/U0 ] -quiet] -quiet